Semiconductor device

ABSTRACT

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 15/066,309filed on Mar. 10, 2016, which is based upon and claims the benefit ofpriority of the prior Japanese Patent Application No. 2015-064027, filedon Mar. 26, 2015, and the Japanese Patent Application No. 2016-017827,filed on Feb. 2, 2016, the entire contents of which are incorporatedherein by reference.

FIELD

The embodiments discussed herein relate to semiconductor devices.

BACKGROUND

One of the semiconductor devices is a nonvolatile memory. For example,there is known a nonvolatile memory that includes, as a memorytransistor, a MOS (Metal Oxide Semiconductor) type field effecttransistor storing information by accumulating charges (hot carriers) inthe sidewall insulating film of a gate electrode sidewall.

For such a nonvolatile memory, there is known a technique of increasingthe thickness of the sidewall insulating film of a transistor includedin a circuit section in the periphery of a memory section including amemory transistor so as to reduce the injection efficiency of hotcarriers of the former transistor.

See, for example, US Patent Application Publication No. 2008/0062745,Japanese Laid-open Patent Publication No. 2008-244097, and JapaneseLaid-open Patent Publication No. 09-252059.

In a nonvolatile memory provided with a memory transistor group storinginformation by accumulating hot carriers in a sidewall insulating film,the programming speed of the entire nonvolatile memory depends on theprogramming speed of the individual memory transistor. If theprogramming speed of the individual memory transistor is not sufficient,then depending on the capacitance of a nonvolatile memory, apredetermined programming might not be able to be performed within atime period allowed on a system including the nonvolatile memory.

SUMMARY

According to an aspect, there is provided a semiconductor deviceincluding a memory region and a logic region, in which the memory regionincludes a first transistor including: a first gate insulating filmprovided above a semiconductor substrate; a first gate electrodeprovided above the first gate insulating film; a first sidewallinsulating film provided on a sidewall of the first gate electrode andabove the semiconductor substrate; and a first source region and a firstdrain region provided in the semiconductor substrate on both sides ofthe first gate electrode, respectively, the first transistor storinginformation by accumulating charge in the first sidewall insulatingfilm, and in which the logic region includes a second transistorincluding: a second gate insulating film provided above thesemiconductor substrate; a second gate electrode provided above thesecond gate insulating film; a second sidewall insulating film providedon a sidewall of the second gate electrode and above the semiconductorsubstrate; and a second source region and second drain region providedin the semiconductor substrate on both sides of the second gateelectrode, respectively, and in which the width of the first sidewallinsulating film is larger than the width of the second sidewallinsulating film.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates an example of a semiconductor device according to afirst embodiment;

FIG. 2 illustrates an example of a semiconductor device according toanother embodiment;

FIGS. 3A and 3B are explanatory views of charge injection into asidewall insulating film of a memory transistor;

FIG. 4 illustrates an example of a semiconductor device according to asecond embodiment;

FIGS. 5A to 5C illustrate the program characteristics of a memorytransistor according to the second embodiment;

FIGS. 6A and 6B illustrate the program characteristics of a memorytransistor according to a comparative example;

FIG. 7 is an explanatory view of the evaluation of the programcharacteristics of the memory transistor according to the secondembodiment;

FIG. 8 is a view (part 1) illustrating an example of the method formanufacturing a semiconductor device according to a third embodiment;

FIG. 9 is a view (part 2) illustrating an example of a method formanufacturing the semiconductor device according to the thirdembodiment;

FIG. 10 is a view (part 3) illustrating an example of the method formanufacturing the semiconductor device according to the thirdembodiment;

FIG. 11 is a view (part 4) illustrating an example of the method formanufacturing the semiconductor device according to the thirdembodiment;

FIG. 12 is a view (part 5) illustrating an example of the method formanufacturing the semiconductor device according to the thirdembodiment;

FIG. 13 is a view (part 6) illustrating an example of the method formanufacturing the semiconductor device according to the thirdembodiment;

FIG. 14 is a view (part 1) illustrating an example of a method formanufacturing a semiconductor device according to a fourth embodiment;

FIG. 15 is a view (part 2) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 16 is a view (part 3) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 17 is a view (part 4) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 18 is a view (part 5) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 19 is a view (part 6) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 20 is a view (part 7) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 21 is a view (part 8) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 22 is a view (part 9) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 23 is a view (part 10) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 24 is a view (part 11) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 25 is a view (part 12) illustrating an example of the method formanufacturing the semiconductor device according to the fourthembodiment;

FIG. 26 is a view (part 1) illustrating an example of a method formanufacturing a semiconductor device according to a fifth embodiment;

FIG. 27 is a view (part 2) illustrating an example of the method formanufacturing the semiconductor device according to the fifthembodiment;

FIG. 28 is a view (part 3) illustrating an example of the method formanufacturing the semiconductor device according to the fifthembodiment;

FIG. 29 is a view (part 4) illustrating an example of the method formanufacturing the semiconductor device according to the fifthembodiment;

FIG. 30 is a view (part 5) illustrating an example of the method formanufacturing the semiconductor device according to the fifthembodiment;

FIG. 31 is a view (part 6) illustrating an example of the method formanufacturing the semiconductor device according to the fifthembodiment;

FIG. 32 illustrates a first configuration example of a semiconductordevice according to a sixth embodiment;

FIG. 33 illustrates a second configuration example of the semiconductordevice according to the sixth embodiment;

FIG. 34 is a view (part 1) illustrating an example of a method formanufacturing a semiconductor device according to a seventh embodiment;

FIG. 35 is a view (part 2) illustrating an example of a method formanufacturing the semiconductor device according to the seventhembodiment;

FIG. 36 is a view (part 1) illustrating an example of a method formanufacturing a semiconductor device according to an eighth embodiment;

FIG. 37 is a view (part 2) illustrating an example of the method formanufacturing the semiconductor device according to the eighthembodiment;

FIG. 38 is a view (part 3) illustrating an example of the method formanufacturing the semiconductor device according to the eighthembodiment;

FIG. 39 is a view (part 4) illustrating an example of the method formanufacturing the semiconductor device according to the eighthembodiment;

FIG. 40 illustrates a memory transistor of a comparative example;

FIG. 41 illustrates an example of a twin-bit cell type nonvolatilememory;

FIG. 42 is an explanatory view of a programming operation of thetwin-bit cell type nonvolatile memory;

FIG. 43 is an explanatory view of a reading operation of the twin-bitcell type nonvolatile memory;

FIG. 44 is an explanatory view of an erasing operation of the twin-bitcell type nonvolatile memory;

FIG. 45 is an explanatory view of the area of the twin-bit cell typenonvolatile memory;

FIG. 46 illustrates an example of a memory transistor according to anembodiment;

FIGS. 47A to 47D illustrate an example of the concentration profile whenphosphorus is used for the impurity of an LDD (Lightly Doped Drain)region;

FIGS. 48A to 48D illustrate an example of the concentration profile whenarsenic is used for the impurity of the LDD region;

FIG. 49 illustrates an example of the programming characteristics of amemory transistor with an SCR (screen) layer;

FIG. 50 illustrates an example of the erasing characteristics of thememory transistor with the SCR layer;

FIGS. 51A and 51B are views (part 1) illustrating the LDD regionconcentration dependence of the programming characteristics of thememory transistor with the SCR layer;

FIGS. 52A and 52B are views (part 2) illustrating the LDD regionconcentration dependence of the programming characteristics of thememory transistor with the SCR layer;

FIGS. 53A and 53B are views (part 3) illustrating the LDD regionconcentration dependence of the programming characteristics of thememory transistor with the SCR layer;

FIG. 54 is a view (part 1) illustrating the SCR layer concentrationdependence and SD region impurity type dependence of the programmingcharacteristics of the memory transistor with the SCR layer;

FIG. 55 is a view (part 2) illustrating the SCR layer concentrationdependence and SD region impurity type dependence of the programmingcharacteristics of the memory transistor with the SCR layer;

FIG. 56 illustrates another example of the programming characteristicsof the memory transistor with the SCR layer;

FIG. 57 illustrates an example of the nonvolatile memory using thememory transistor with the SCR layer;

FIGS. 58A and 58B are explanatory views of the programming operation ofthe nonvolatile memory using the memory transistor with the SCR layer;

FIGS. 59A and 59B are explanatory views of the reading operation of thenonvolatile memory using the memory transistor with the SCR layer;

FIGS. 60A and 60B are explanatory views of the erasing operation of thenonvolatile memory using the memory transistor with the SCR layer;

FIG. 61 is a view (part 1) illustrating an example of the method formanufacturing the nonvolatile memory;

FIG. 62 is a view (part 2) illustrating an example of the method formanufacturing the nonvolatile memory;

FIG. 63 is a view (part 3) illustrating an example of the method formanufacturing the nonvolatile memory;

FIG. 64 is a view (part 4) illustrating an example of the method formanufacturing the nonvolatile memory;

FIG. 65 is a view (part 5) illustrating an example of the method formanufacturing the nonvolatile memory;

FIG. 66 is a view (part 1) illustrating another example of the methodfor manufacturing the nonvolatile memory;

FIG. 67 is a view (part 2) illustrating another example of the methodfor manufacturing the nonvolatile memory;

FIG. 68 is a view (part 3) illustrating another example of the methodfor manufacturing the nonvolatile memory;

FIG. 69 is a view (part 4) illustrating another example of the methodfor manufacturing the nonvolatile memory;

FIG. 70 is a view (part 5) illustrating another example of the methodfor manufacturing the nonvolatile memory;

FIG. 71 is a view (part 6) illustrating another example of the methodfor manufacturing the nonvolatile memory; and

FIG. 72 is an explanatory view of the memory transistor with the SCRlayer.

DESCRIPTION OF EMBODIMENTS

Several embodiments will be described below with reference to theaccompanying drawings, wherein like reference numerals refer to likeelements throughout.

First, a first embodiment will be described.

FIG. 1 illustrates an example of a semiconductor device according to thefirst embodiment. FIG. 1 schematically illustrates an exemplary crosssection of a main part of the semiconductor device according to thefirst embodiment.

A semiconductor device 1A illustrated in FIG. 1 is an example of thenonvolatile memory, and includes a transistor (memory transistor) 10provided in a memory region 10 a and a transistor (logic transistor) 20provided in a logic region 20 a. The memory transistor 10 and the logictransistor 20 are formed (mixedly mounted) on a p-type or n-type commonsemiconductor substrate 2. Various types of semiconductor substrates,such as a silicon (Si) substrate or a silicon germanium (SiGe)substrate, may be used for the semiconductor substrate 2. A region(element region) in which the memory transistor 10 is formed and aregion (element region) in which the logic transistor 20 is formed aredefined by an element isolating region 3 that is formed in thesemiconductor substrate 2 using STI (Shallow Trench Isolation), thermaloxidation, or the like.

Note that, although one memory transistor 10 is illustrated in FIG. 1,the memory region 10 a of the semiconductor device 1A may include aplurality of memory transistors 10, or include at least one memorytransistor 10 and another memory transistor. Although one logictransistor 20 is illustrated in FIG. 1, the logic region 20 a of thesemiconductor device 1A may include a plurality of logic transistors 20,or at least one logic transistor 20 and another logic transistor.

As illustrated in FIG. 1, the memory transistor 10 includes a gateinsulating film 11 provided above the semiconductor substrate 2, a gateelectrode 12 provided above the gate insulating film 11, and a sidewallinsulating film 13 provided on the sidewall of the gate electrode 12 andabove the semiconductor substrate 2. The memory transistor 10 furtherincludes an impurity region 14 a and an impurity region 14 b that areprovided in the semiconductor substrate 2 on both sides (both sides inthe gate length direction) of the gate electrode 12, respectively, andfunction as a source region or drain region. The memory transistor 10may also include an LDD (Lightly Doped Drain) region 15 a and an LDDregion 15 b on the inner side of the impurity region 14 a and theimpurity region 14 b which function as the source region or drain regionin the semiconductor substrate 2 below the sidewall insulating film 13.

Here, various types of insulating materials, such as silicon oxide(SiO₂), silicon nitride (Si₃N₄), and hafnium oxide (HfO₂), may be usedfor the gate insulating film 11. The film thickness of the gateinsulating film 11 is set, for example, based on the threshold voltageset for the memory transistor 10.

Metals, such as titanium (Ti), tungsten (W), and the nitrides thereof,other than polysilicon, may be used for the gate electrode 12.

The sidewall insulating film 13 includes a stacked structure of an oxidefilm 13 a and a nitride film 13 b that are insulating films, forexample. Silicon oxide is used for the oxide film 13 a, for example.Silicon nitride is used for the nitride film 13 b, for example. Forexample, the oxide film 13 a is provided so as to have an L-shaped crosssection, on the sidewall of the gate electrode 12 and on thesemiconductor substrate 2, and the nitride film 13 b is provided on theoxide film 13 a. Although the sidewall insulating film 13 having atwo-layer structure of the oxide film 13 a and nitride film 13 b isillustrated in FIG. 1, the sidewall insulating film 13 may be made tohave a three-layer structure obtained by further providing an oxide filmabove the oxide film having an L-shaped cross section and the nitridefilm, or may be made to have a stacked structure of four or more layersof insulating films. Other than this, it is also possible to make thesidewall insulating film 43 have a single-layer structure of an oxidefilm or nitride film. The sidewall insulating film 13 is provided sothat a width (thickness) W1 in the gate length direction of the gateelectrode 12 (in the plane direction of the semiconductor substrate 2)is set to be larger than a width (thickness) W2 of a sidewall insulatingfilm 23 (to be described later) of the logic transistor 20.

The impurity region 14 a and impurity region 14 b contain apredetermined concentration of the impurity of a predeterminedconductivity type, i.e., an n-type impurity, such as phosphorus (P) orarsenic (As), or a P-type impurity, such as boron (B).

The LDD region 15 a and LDD region 15 b contain the impurity of the sameconductivity type as the conductivity type of the impurity contained inthe impurity region 14 a and impurity region 14 b, in a lowerconcentration than the impurity region 14 a and impurity region 14 b.

In the memory transistor 10, a region between the impurity region 14 aand the impurity region 14 b (or between the LDD region 15 a and the LDDregion 15 b) below the gate electrode 12 functions as a channel region16 in which a carrier (electron or hole) moves.

The memory transistor 10 is a nonvolatile memory transistor that storesinformation by accumulating charges (electrons or the holes) in thesidewall insulating film 13. In the memory transistor 10 with thesidewall insulating film 13 including a stacked structure of the oxidefilm 13 a and nitride film 13 b, the charge is accumulated mainly in thenitride film 13 b. The nitride film 13 b of silicon nitride or the likehas a charge trap level, while the oxide film 13 a of silicon oxide orthe like suppresses the scattering of charges accumulated in the nitridefilm 13 b.

As illustrated in FIG. 1, the logic transistor 20 includes a gateinsulating film 21 provided above the semiconductor substrate 2, a gateelectrode 22 provided above the gate insulating film 21, and a sidewallinsulating film 23 provided on the sidewall of the gate electrode 22 andabove the semiconductor substrate 2. The logic transistor 20 furtherincludes an impurity region 24 a and an impurity region 24 b which areprovided in the semiconductor substrate 2 on both sides (both sides inthe gate length direction) of the gate electrode 22, respectively, andwhich function as a source region or drain region. The logic transistor20 may also include an LDD region 25 a and an LDD region 25 b on theinner side of the impurity region 24 a and impurity region 24 b whichfunction as the source region or drain region in the semiconductorsubstrate 2 below the sidewall insulating film 23.

Here, various types of insulating materials, such as silicon oxide,silicon nitride, and hafnium oxide, may be used for the gate insulatingfilm 21. The film thickness of the gate insulating film 21 is set, forexample, based on the threshold voltage set for the logic transistor 20.

Metals, such as titanium, and the nitrides thereof other thanpolysilicon, may be used for the gate electrode 22.

The sidewall insulating film 23 includes an oxide film of silicon oxideor the like, or a nitride film of silicon nitride or the like. Thesidewall insulating film 23 does not necessarily need to include astacked structure of an oxide film and a nitride film, and therefore maybe made to have a single-layer structure of an insulating film, such asan oxide film or a nitride film. The sidewall insulating film 23 isprovided so that the width (thickness) W2 in the gate length directionof the gate electrode 22 (in the plane direction of the semiconductorsubstrate 2) is set to be smaller than the width W1 of the sidewallinsulating film 13 of the memory transistor 10.

The impurity region 24 a and impurity region 24 b contain an impurity ofan n-type or p-type conductivity, in a predetermined concentration.

The LDD region 25 a and LDD region 25 b contain the impurity of the sameconductivity type as the conductivity type of the impurity contained inthe impurity region 24 a and impurity region 24 b, in a lowerconcentration than the impurity region 24 a and impurity region 24 b.

In the logic transistor 20, a region between the impurity region 24 aand the impurity region 24 b (or between the LDD region 25 a and the LDDregion 25 b) below the gate electrode 22 functions as a channel region26 in which a carrier (electron or hole) moves.

The logic transistor 20 of the logic region 20 a is used, for example,in order to perform programming (write-in) and reading (read-out)operations on the memory transistor 10 of the memory region 10 a.

Each of the programming and reading operations of the memory transistor10 is performed as follows.

First, the programming operation is performed by setting each node ofthe gate electrode 12, impurity region 14 a, impurity region 14 b, andsemiconductor substrate 2 to a predetermined potential to generate hotcarriers, and injecting the generated hot carriers into the sidewallinsulating film 13 for accumulation (retention).

Now, assume that the memory transistor 10 is of an n-channel type, thesemiconductor substrate 2 (channel region 16 during non-operation) is ofa p-type, and the impurity region 14 a and impurity region 14 b (the LDDregion 15 a and LDD region 15 b) are of an n-type.

If electrons are injected into the sidewall insulating film 13 (13 d) onthe impurity region 14 b side, the impurity region 14 a (source) and thesemiconductor substrate 2 are grounded and a positive voltage is appliedto the gate electrode 12 and the impurity region 14 b (drain), forexample. Alternatively, a negative voltage may be applied to thesemiconductor substrate 2. If these potentials are adjusted in thismanner, then in the re-channel memory transistor 10, an inversion layer(not illustrated) is formed in the channel region 16 and thus electronsflow through the channel region 16 from the impurity region 14 a towardthe impurity region 14 b. The electrons flowing through the channelregion 16 toward the impurity region 14 b become in a high energy statein a vicinity of the impurity region 14 b due to the electric fieldcaused by the positive voltage applied to the impurity region 14 b,thereby generating hot electrons. The hot electrons generated in thevicinity of the impurity region 14 b are injected and accumulated intothe sidewall insulating film 13 d on the impurity region 14 b side bythe electric field caused by the positive voltage applied to the gateelectrode 12.

The reading operation in the n-channel memory transistor 10 is performedby grounding the impurity region 14 b (source) and semiconductorsubstrate 2 and applying a positive voltage to the gate electrode 12 andthe impurity region 14 a (drain), for example. If electrons are alreadyinjected and accumulated into the sidewall insulating film 13 d on theimpurity region 14 b side, positive charges are induced to a region,e.g., the LDD region 15 b, below the sidewall insulating film 13 toincrease the resistance of the LDD region 15 b. Therefore, the electriccurrent flowing from the impurity region 14 a to the impurity region 14b will decrease. If electrons are not yet injected and accumulated intothe sidewall insulating film 13 d on the impurity region 14 b side, theresistance of a region, e.g., the LDD region 15 b, below the sidewallinsulating film 13 will not increase and thus the electric currentflowing from the impurity region 14 a to the impurity region 14 b willnot decrease either. As described above, depending on the electriccurrent flowing from the impurity region 14 a to the impurity region 14b, the presence or absence (information of “0” or “1”) of electrons ofthe sidewall insulating film 13 d is read out.

When the programming operation is performed for injecting electrons intothe sidewall insulating film 13 (13 c) on the impurity region 14 a side,the voltages (source and drain voltages) applied to the impurity region14 a and impurity region 14 b may be switched from the voltages appliedduring the above-described programming operation. Moreover, similarlywhen the reading operation is performed for reading out the presence orabsence of electrons of the sidewall insulating film 13 c, the voltages(source and drain voltages) applied to the impurity region 14 a andimpurity region 14 b may be switched from the voltages applied duringthe above-described reading operation.

The memory transistor 10 is used as a memory cell for storing 2-bitinformation depending on the presence or absence of injected electronsof each of the sidewall insulating film 13 c and the sidewall insulatingfilm 13 d.

When the memory transistor 10 is set to a p-channel type, thesemiconductor substrate 2 (channel region 16 during non-operation) isset to an n-type and the impurity region 14 a and impurity region 14 b(the LDD region 15 a and LDD region 15 b) are set to p-types.

In the p-channel memory transistor 10, holes are injected andaccumulated into the sidewall insulating film 13, for example, byapplying to each node a voltage having the opposite sign of the voltagethat is applied during the above-described programming operation. In thep-channel memory transistor 10, the presence or absence of holes in thesidewall insulating film 13 is read out by applying to each node avoltage having the opposite sign of the voltage that is applied duringthe above-described reading operation, for example.

Next, the sidewall insulating film 13 and sidewall insulating film 23 ofthe above-described memory transistor 10 and logic transistor 20 aredescribed.

First, for comparison, an example of a semiconductor device according toanother embodiment is illustrated in FIG. 2, in which the width of thesidewall insulating film of the memory transistor is made equal to thewidth of the sidewall insulating film of the logic transistor.

A semiconductor device 100 illustrated in FIG. 2 differs from thesemiconductor device 1A according to the first embodiment illustrated inthe above FIG. 1, in that the semiconductor device 100 includes a memorytransistor 110 provided with a sidewall insulating film 113 having thesame width W2 as the sidewall insulating film 23 of the logic transistor20.

The LDD region 15 a and LDD region 15 b have an effect of suppressing avariation in the generation of hot carriers and the injection of hotcarriers into sidewall insulating film 13 (13 c, 13 d) during theprogramming operation, thereby achieving a small variation in theprogramming speed. Also in the semiconductor device 100 illustrated inFIG. 2, the provision of the LDD region 15 a and LDD region 15 bachieves a small variation in the programming speed as compared with thecase where these LDD region 15 a and LDD region 15 b are not provided.However, even if such LDD region 15 a and LDD region 15 b are provided,a sufficient programming speed needed for the semiconductor device 100is sometimes not obtained. When the memory capacity in a memory region110 a (nonvolatile memory) including a plurality of memory transistors110 is relatively small, the programming time as a whole falls within anacceptable level even if the programming speed of the individual memorytransistor 110 (memory cell) is relatively slow. However, when thememory capacity becomes relatively large, the programming time as awhole sometimes does not fall within the acceptable level.

One of the techniques for increasing the programming speed is atechnique for generating more hot carriers. To this end, the electricfield below the sidewall insulating film 13 may be increased and theimpurity concentration of the channel region 16 may be increased.However, if the impurity concentration of the channel region 16 isincreased in this manner, inconveniently the threshold voltage of thememory transistor 110 will increase and the read current will decrease.

On the other hand, in the semiconductor device 1A illustrated in theabove FIG. 1, the width W1 of the sidewall insulating film 13 of thememory transistor 10 is set to be larger than the width W2 of thesidewall insulating film 23 of the logic transistor 20. Accordingly, avariation of the resistance in the region below the sidewall insulatingfilm 13 when hot carriers are injected into the sidewall insulating film13 will easily occur, so that an improvement in the programming speedwill be achieved.

FIGS. 3A and 3B are explanatory views of charge injection into thesidewall insulating film of the memory transistor. FIG. 3A illustratesan example of the charge injection into the relatively narrow sidewallinsulating film, while FIG. 3B illustrates an example of the chargeinjection into the relatively wide sidewall insulating film. That is,FIG. 3A corresponds to an example of the charge injection into thesidewall insulating film 113 of the memory transistor 110 illustrated inthe above FIG. 2. FIG. 3B corresponds to an example of the chargeinjection into the sidewall insulating film 13 of the memory transistor10 illustrated in the above FIG. 1.

In FIG. 3A, the impurity regions 14 a, 14 b and impurity regions 24 a,24 b which are high-concentration source/drain diffusion layers areformed by impurity ion implantation after formation of the sidewallinsulating film 113 and sidewall insulating film 23. Subsequentactivation annealing laterally diffuses the impurities to below thesidewall insulating film 113 and sidewall insulating film 23. The widthW2 of the sidewall insulating film 23 of the logic transistor 20 is setso that the impurity regions 24 a, 24 b will laterally diffuse but notto reach below the gate electrode 22. If the width W2 of the sidewallinsulating film 23 is larger than needed, a parasitic resistance willincrease and the performance will degrade. On the other hand, if thewidth of the sidewall insulating film 113 of the memory transistor 110is set to the same as the width W2 of the sidewall insulating film 23 ofthe logic transistor 20, the impurity concentration below the sidewallinsulating film 113 will become higher than needed due to the lateraldiffusion of the impurity regions 14 a, 14 b and thus will be hardlyaffected by charges 13 e accumulated in the sidewall insulating film113. As a result, more charges 13 e need to be injected into thesidewall insulating film 113 and thus it will take a longer time toprogram.

In contrast, in FIG. 3B, the width of the sidewall insulating film 13 ofthe memory transistor 10 is set to the width W1 larger than the width W2of the sidewall insulating film 23 of the logic transistor 20.Accordingly, even if impurities of the impurity regions 14 a, 14 b thatare formed by ion implantation after formation of the sidewallinsulating film 13 laterally diffuse, the LDD regions 15 a, 15 b will bepresent having a sufficiently large width below the sidewall insulatingfilm 13. As a result, a change in resistance when the charge 13 e isinjected into the sidewall insulating film 13 will increase even if thecharge amount is the same, so that the programming time will be reduced.

The same is true of both the injection of electrons and the injection ofholes into the sidewall insulating film 113 and the sidewall insulatingfilm 13.

The width W1 of the sidewall insulating film 13 of the memory transistor10 is set to be larger than the width W2 of the sidewall insulating film23 of the logic transistor 20 that is mixedly mounted in thesemiconductor substrate 2 together with the memory transistor 10.

A wider width of the sidewall insulating film 13 is better from theabove-described viewpoint, but actually the width of the sidewallinsulating film 13 is limited to the width from the sidewall of the gateelectrode 12 to a plug (not illustrated) connected to the impurityregion 14 a and impurity region 14 b. Note that, by the amount of anincrease in the width of the sidewall insulating film 13, the elementregion of the memory transistor 10 may be expanded and the impurityregion 14 a and impurity region 14 b may be shifted in the directionaway from the gate electrode 12. However, in this case, an increase inthe size of the memory region 10 a including a group of memorytransistors 10 and an increase in the size of the semiconductor device1A including the memory region 10 a need to be taken into consideration.

For the purpose of increasing the programming speed of the memorytransistor 10, the film thickness of the oxide film 13 a may be thinnedin addition to setting the width W1 of the sidewall insulating film 13to be larger than the width W2 of the sidewall insulating film 23 of thelogic transistor 20. By thinning the film thickness of the oxide film 13a provided mainly between the nitride film 13 b, into which charges areinjected, and the semiconductor substrate 2 in this manner, theinjection probability of hot carriers will increase and therefore animprovement in the programming speed is achieved. However, note that,the thinner the film thickness of the oxide film 13 a, the more easilythe injected charges will dissipate and data retention characteristicmay degrade.

Note that, if the width W2 of the sidewall insulating film 23 isincreased on the logic transistor 20 side, the injection probability ofhot carriers into the sidewall insulating film 23 of the logictransistor 20 may be reduced. However, because an increase of the widthW2 of the sidewall insulating film 23 increases the length of the LDDregion 25 a and LDD region 25 b and increases the parasitic resistance,the transistor performance will degrade.

Next, a second embodiment will be described.

FIG. 4 illustrates an example of a semiconductor device according to thesecond embodiment. FIG. 4 schematically illustrates an exemplary crosssection of a main part of the semiconductor device according to thesecond embodiment.

A semiconductor device 1B illustrated in FIG. 4 is an example of thenonvolatile memory, and includes a transistor (memory transistor) 40provided in a memory region 40 a. The memory transistor 40 is formed onthe semiconductor substrate 2 of a p-type or n-type. Various types ofsemiconductor substrates, such as a silicon substrate, may be used forthe semiconductor substrate 2. The region (element region) in which thememory transistor 40 is formed is defined by the element isolatingregion 3 that is formed in the semiconductor substrate 2 using STI orthe like.

Note that, although one memory transistor 40 is illustrated in FIG. 4,the memory region 40 a of the semiconductor device 1B may include aplurality of memory transistors 40, or at least one memory transistor 40and another memory transistor.

As illustrated in FIG. 4, the memory transistor 40 includes a gateinsulating film 41 provided above the semiconductor substrate 2, a gateelectrode 42 provided above the gate insulating film 41, and a sidewallinsulating film 43 provided on the sidewall of the gate electrode 42 andabove the semiconductor substrate 2. The memory transistor 40 furtherincludes an impurity region 44 a and an impurity region 44 b which areprovided in the semiconductor substrate 2 on both sides (both sides inthe gate length direction) of the gate electrode 42, respectively, andfunction as a source region or drain region. The memory transistor 40may include an LDD region 45 a and an LDD region 45 b on the inner sideof the impurity region 44 a and impurity region 44 b in thesemiconductor substrate 2 below the sidewall insulating film 43. Thememory transistor 40 further includes a channel region 46 provided in aregion between the impurity region 44 a and the impurity region 44 b (orbetween the LDD region 45 a and the LDD region 45 b) below the gateelectrode 42 and an impurity region 47 provided below the channel region46.

Here, various types of insulating materials, such as a silicon oxide,may be used for the gate insulating film 41. The film thickness of thegate insulating film 41 is set, for example, based on the thresholdvoltage, programming voltage, and erasing voltage set for the memorytransistor 40.

Various types of conductive materials, such as polysilicon, may be usedfor the gate electrode 42.

The sidewall insulating film 43 includes a stacked structure of an oxidefilm 43 a of silicon oxide or the like and a nitride film 43 b ofsilicon nitride or the like. For example, the oxide film 43 a isprovided so as to have an L-shaped cross section, on the sidewall of thegate electrode 42 and on the semiconductor substrate 2, and the nitridefilm 43 b is provided on the oxide film 43 a. The sidewall insulatingfilm 43 may have a three-layer structure obtained by further providingan oxide film on the oxide film having an L-shaped cross section and thenitride film, or may have a stacked structure of four or more layers ofinsulating films. Other than this, the sidewall insulating film 43 mayhave a single-layer structure of an oxide film or nitride film.

The impurity region 44 a and impurity region 44 b contain an impurity ofan n-type or p-type conductivity, in a predetermined concentration.

The LDD region 45 a and LDD region 45 b contain the impurity of the sameconductivity type as the conductivity type of the impurity contained inthe impurity region 44 a and impurity region 44 b, in a concentrationlower than the concentration of the impurity region 44 a and impurityregion 44 b.

The channel region 46 is a non-doped region where no impurity isintentionally added, or a region where an extremely low concentration ofimpurity is contained. The impurity concentration of the channel region46 is set to be equal to or less than 1×10¹⁷ cm⁻³, for example.

The impurity region 47 is a region that is provided below the channelregion 46 and contains a higher concentration of impurity than thechannel region 46. The impurity region 47 is also referred to as ascreen layer. The impurity region 47 contains, in a predeterminedconcentration, an impurity of a conductivity type different from theconductivity type of the impurity contained in the impurity region 44 aand impurity region 44 b which function as the source region or drainregion. The threshold voltage of the memory transistor 40 is controlledby the impurity concentration of the impurity region 47. Moreover, theimpurity region 47 suppresses the punch through between the impurityregion 44 a and impurity region 44 b which function as the source regionor drain region. Because the impurity region 47 is embedded into thesemiconductor substrate 2 by the amount of the thickness of the channelregion 46 from the interface between the semiconductor substrate 2 andthe gate insulating film 41 and the impurity concentration of theimpurity region 47 adjusts the threshold voltage, the impurityconcentration of the impurity region 47 is set to be relatively high, onthe order of 1×10¹⁹ cm⁻³, for example.

The memory transistor 40 is a nonvolatile memory transistor that storesinformation by accumulating charges (electrons or holes) into thesidewall insulating film 43.

Each of the programming operation and reading operation of the memorytransistor 40 may be performed as with the memory transistor 10described in the first embodiment. That is, the each operation isperformed by setting each node of the gate electrode 42, impurity region44 a, impurity region 44 b, and semiconductor substrate 2 to apredetermined potential to generate hot carriers, and injecting andaccumulating the generated hot carriers in the sidewall insulating film43.

In the memory transistor 40, the threshold voltage is controlled by theimpurity concentration of the impurity region 47 embedded into thesemiconductor substrate 2, and the impurity concentration of the channelregion 46 above the impurity region 47 is set to be lower. In the memorytransistor 40, the impurity concentration of the channel region 46 isnot increased but the impurity concentration of the impurity region 47below the channel region 46 is increased so as to increase thegeneration of hot carriers during the programming operation. Because theimpurity region 47 is located away from the interface between thesemiconductor substrate 2 and the gate insulating film 41, the thresholdvoltage of the memory transistor 40 will not significantly increase evenif the impurity concentration of the impurity region 47 is increased.

That is, in a memory transistor not provided with such an impurityregion 47, if the impurity concentration of the channel region isincreased in order to increase the generation of hot carriers,inconveniently the threshold voltage may increase and the read currentmay decrease. In contrast, in the memory transistor 40 having therelatively high-concentration impurity region 47 provided below thechannel region 46 as described above, it is possible to increase thegeneration of hot carriers and control the threshold voltage withoutcausing such inconvenience.

In order to effectively realize the functions, such as increasing thegeneration of hot carriers, controlling the threshold voltage, andsuppressing the punch-through, the impurity region 47 is provided so asto contact the impurity region 44 a and impurity region 44 b whichfunction as the source region or drain region.

In the memory transistor 40, an improvement in the programming speed isachieved by adopting the impurity region 47 as described above.

FIGS. 5A to 5C illustrate the program characteristics of the memorytransistor according to the second embodiment. FIG. 5A schematicallyillustrates a configuration example of the memory transistor accordingto the second embodiment, while FIGS. 5B and 5C illustrate an example ofthe relationship between the gate voltage Vg[V] and the read current(drain current) Id[A], respectively. FIGS. 6A and 6B illustrate theprogram characteristics of a memory transistor according to acomparative example. FIG. 6A schematically illustrates a configurationexample of the memory transistor according to the comparative example,while FIG. 6B illustrates an example of the relationship between thegate voltage Vg[V] and the read current (drain current) Id[A].

In the memory transistor 40 illustrated in FIG. 5A, the film thicknessof the gate insulating film 41 is set to 7 nm, the gate length Lg of thegate electrode 42 to 0.1 μm or 0.5 μm, and the width of the sidewallinsulating film 43 to 74 nm. The LDD region 45 a and LDD region 45 b areformed by implanting phosphorus from four directions under theconditions: the accelerating energy of 35 keV and the dose amount of2.5×10¹² cm⁻², while the impurity region 44 a and impurity region 44 bare formed so as to have a concentration sufficiently higher than2.5×10¹² cm⁻². The channel region 46 is formed as a non-doped layer,while the impurity region 47 provided in the semiconductor substrate 2below the channel region 46 is formed by implanting boron under theconditions: the accelerating energy of 20 keV and the dose amount of2.4×10¹³ cm⁻².

The programming operation with respect to the memory transistor 40 isperformed under the voltage conditions where both the impurity region 44a (source) and the semiconductor substrate 2 are set to 0 V and both thegate electrode 42 and the impurity region 44 b (drain) are set to 4.5 V.After the programming operation is performed with a programming time Tpset to 1 ms, 100 μs, and 10 μs under these voltage conditions, thereading operation is performed by setting the impurity region 44 b(source) and the semiconductor substrate 2 to 0 V and applying apositive voltage to the gate electrode 42 and impurity region 44 a(drain). Here, the voltage of the impurity region 44 a is 0.5 V, forexample. The relationship between the gate voltage Vg and the readcurrent Id flowing from the drain to the source during the readingoperation is illustrated in FIG. 5B (in the case of the gate length of0.1 μm) and in FIG. 5C (in the case of the gate length of 0.5 μm). Theread current Id (initial) before programming is also illustrated inFIGS. 5B and 5C.

In a memory transistor 40A illustrated in FIG. 6A, the gate length Lg ofthe gate electrode 42 is set to 0.35 μm, and a channel region (referredto as a “flat channel region” for convenience) 46A with a predetermineddepth from the surface of the semiconductor substrate 2 is provided. Theflat channel region 46A is formed by implanting boron under thecondition of a relatively-low dose amount of 3.2×10¹² cm⁻². The otherconfigurations are the same as the memory transistor 40 of FIG. 5A.

The programming operation with respect to the memory transistor 40A isalso performed under the same voltage and programming time conditions asthe programming operation of the memory transistor 40 of FIG. 5A, andsubsequently the reading operation is performed. The relationshipbetween the gate voltage Vg and the read current Id flowing from thedrain to the source during the reading operation is illustrated in FIG.6B. The read current (initial) before programming is also illustrated inFIG. 6B.

In the memory transistor 40 of FIG. 5A having the relatively-highconcentration impurity region 47 provided below the channel region 46,the programming is performed even if the programming time Tp decreasesby one digit or more, such as from 1 ms to 100 μs and 10 μs, asillustrated in FIGS. 5B and 5C.

On the other hand, in the memory transistor 40A of FIG. 6A provided withthe flat channel region 46A, the IV characteristic does not change atall even with the programming time Tp of 1 ms as illustrated in FIG. 6Band thus the programming is not performed. FIG. 6B indicates that allthe IV characteristics, initial, after 10 μs, after 100 μs, and after 1ms overlap with each other and do not vary, i.e., the programming is notperformed at all. In the memory transistor 40A provided with the flatchannel region 46A, a higher voltage needs to be applied in order toprogram, and even if such a higher voltage is applied, the programmingspeed is slow as compared with the memory transistor 40.

FIG. 7 is an explanatory view of the evaluation of the programcharacteristics of the memory transistor according to the secondembodiment. The horizontal axis of FIG. 7 represents a programmingvoltage Vp[V], while the vertical axis of FIG. 7 represents a ratio(current ratio) R[%] between a read current detected after performingthe programming operation for a certain period of time and a readcurrent before programming.

According to FIG. 7, in the memory transistor 40 (FIG. 5A) provided withthe impurity region 47, the current ratios R after performing theprogramming operation under the conditions; the programming voltageVp=3.5 V and the programming time Tp=1 ms, Vp=4.0 V and Tp=100 μs, andVp=4.5 V and Tp=10 μs, respectively, are on the order of 30% andsubstantially equal. That is, in the memory transistor 40, as theprogramming voltage Vp increases by 0.5 V, the programming speedincreases by one digit.

In such a memory transistor 40 provided with the relatively-highconcentration impurity region 47 below the channel region 46, asignificant improvement in the programming speed may be achieved.

Next, a third embodiment will be described.

Here, as the third embodiment, a semiconductor device including thememory transistor 10 and logic transistor 20 described in the abovefirst embodiment and an I/O transistor will be described.

FIGS. 8 to 13 illustrate an example of the method for manufacturing thesemiconductor device according to the third embodiment. Here, FIG. 8 isan exemplary cross sectional schematic view of a main portion of thefirst manufacturing step, FIG. 9 is an exemplary cross sectionalschematic view of the main portion of the second manufacturing step,FIG. 10 is an exemplary cross sectional schematic view of the mainportion of the third manufacturing step, FIG. 11 is an exemplary crosssectional schematic view of the main portion of the fourth manufacturingstep, FIG. 12 is an exemplary cross sectional schematic view of the mainportion of the fifth manufacturing step, and FIG. 13 is an exemplarycross sectional schematic view of the main portion of the sixthmanufacturing step. Hereinafter, an example of the manufacturing stepsof the semiconductor device according to the third embodiment will besequentially described with reference to FIGS. 8 to 13.

First, as illustrated in FIG. 8, the element isolating region 3 thatdefines an element region 10 b of the memory transistor 10 (FIG. 13), anelement region 20 b of the logic transistor 20 (FIG. 13), and an elementregion 30 b of an I/O transistor 30 (FIG. 13) is formed in thesemiconductor substrate 2 using STI. A well region 6 is formed in thesemiconductor substrate 2 before or after formation of the elementisolating region 3. The well region 6 is of a p-type, for example. Afterformation of the well region 6 and element isolating region 3, impurityimplantationation (channel-impurity implantationation) for adjustingeach threshold voltage of the memory transistor 10, the logic transistor20, and the I/O transistor 30 is performed.

Subsequently, an oxide film is formed, for example, with a filmthickness of 7 nm on the semiconductor substrate 2 using thermaloxidation, the oxide film formed in the element region 20 b of the logictransistor 20 is removed, and an oxide film is formed, for example, witha film thickness of 1.8 nm on the semiconductor substrate 2 usingthermal oxidation again. Accordingly, as illustrated in FIG. 8, the gateinsulating film 11, the gate insulating film 21, and a gate insulatingfilm 31 each having a predetermined film thickness are formed in theelement region 10 b of the memory transistor 10, in the element region20 b of the logic transistor 20, and in the element region 30 b of theI/O transistor 30, respectively.

After formation of the gate insulating film 11, gate insulating film 21,and gate insulating film 31, a polysilicon 4 that is a gate electrodematerial is formed, for example, with a film thickness of 100 nm asillustrated in FIG. 8.

Next, as illustrated in FIG. 9, a resist material is formed on thepolysilicon 4, and then a region, in which the gate electrode 12 of thememory transistor 10 is formed, and a resist pattern 5 a that covers theelement region 20 b and element region 30 b are formed by performingexposure and development. With the resist pattern 5 a used as a mask,the polysilicon 4 is etched to form the gate electrode 12 of the memorytransistor 10.

After formation of the gate electrode 12, the resist pattern 5 a isremoved, and then with the gate electrode 12 and polysilicon 4 remainingon the semiconductor substrate 2 used as a mask, impurity implantationis performed on the semiconductor substrate 2 of the element region 10b. With this impurity implantation, the LDD region 15 a and LDD region15 b are formed in the semiconductor substrate 2 on both sides of thegate electrode 12 as illustrated in FIG. 10. The LDD region 15 a and LDDregion 15 b are formed by implanting, for example, arsenic that is ann-type impurity under the conditions: the accelerating energy of 10 keVand the dose amount of 1×10¹³ cm⁻². The channel region 16 of the memorytransistor 10 is formed between the LDD region 15 a and the LDD region15 b.

After formation of the LDD region 15 a and LDD region 15 b, the oxidefilm 13 a is first formed so as to cover the exposed gate electrode 12,polysilicon 4, and gate insulating film 11, and then the nitride film 13b is formed on the oxide film 13 a. For example, the oxide film 13 a isformed with a film thickness of 10 nm, and the nitride film 13 b isformed with a film thickness of 150 nm on the oxide film 13 a. Then, theformed oxide film 13 a and nitride film 13 b are etched back so as toform the sidewall insulating film 13 of the memory transistor 10 havingthe predetermined width W1 on the sidewall of the gate electrode 12 ofthe element region 10 b and above the semiconductor substrate 2 asillustrated in FIG. 11. Note that the sidewall insulating film 13 issimilarly formed also on the sidewall of the polysilicon 4 except thegate electrode 12 and above the semiconductor substrate 2 (on theelement isolating region 3).

After formation of the sidewall insulating film 13, a resist material isformed across the surface, and then exposure and development areperformed. Accordingly, as illustrated in FIG. 12, a resist pattern 5 bis formed which covers the element region 10 b, a region where the gateelectrode 22 of the logic transistor 20 is formed, and a region wherethe gate electrode 32 of the I/O transistor 30 is formed. With theresist pattern 5 b used as a mask, the polysilicon 4 is etched to formthe gate electrode 22 of the logic transistor 20 and the gate electrode32 of the I/O transistor 30. Note that FIG. 12 illustrates a form inwhich a part (edge) of the polysilicon 4 also remains on the elementisolating region 3.

After formation of the gate electrode 22 and gate electrode 32, theresist pattern 5 b is removed, and then impurity implantation isperformed on the semiconductor substrate 2 of the element region 20 band element region 30 b, respectively. By the above impurityimplantation, respectively, the LDD region 25 a and LDD region 25 b areformed in the semiconductor substrate 2 on both sides of the gateelectrode 22, and the LDD region 35 a and LDD region 35 b are formed inthe semiconductor substrate 2 on both sides of the gate electrode 32, asillustrated in FIG. 13. The LDD region 25 a and LDD region 25 b areformed by implanting, for example, arsenic that is an n-type impurityunder the conditions: the accelerating energy of 1.5 keV and the doseamount of 1×10¹⁵ cm⁻². The LDD region 35 a and LDD region 35 b areformed by implanting, for example, phosphorus that is an n-type impurityunder the conditions: the accelerating energy of 35 keV and the doseamount of 1×10¹³ cm⁻². The channel region 26 of the logic transistor 20is formed between the LDD region 25 a and the LDD region 25 b, and thechannel region 36 of the I/O transistor 30 is formed between the LDDregion 35 a and LDD region 35 b.

Next, an insulating film, e.g., a silicon oxide film, is formed with afilm thickness of 80 nm, which is then etched back. Accordingly, asillustrated in FIG. 13, the sidewall insulating film 23 of the logictransistor 20 having the predetermined width W2 is formed on thesidewall of the gate electrode 22 of the element region 20 b and abovethe semiconductor substrate 2. At the same time, the sidewall insulatingfilm 33 of the I/O transistor 30 is formed on the sidewall of the gateelectrode 32 of the element region 30 b and above the semiconductorsubstrate 2. The sidewall insulating film 23 of the logic transistor 20and the sidewall insulating film 33 of the I/O transistor 30 are formedso as to have the predetermined width W2 that is smaller than the widthW1 of the sidewall insulating film 13 of the memory transistor 10. Notethat the sidewall insulating film 23 (or 33) is similarly formed also onthe sidewall of the polysilicon 4 remaining on the element isolatingregion 3.

Subsequently, with the gate electrode 12 and the sidewall insulatingfilm 13 of the sidewall thereof, the gate electrode 22 and the sidewallinsulating film 23 of the sidewall thereof, and the gate electrode 32and the sidewall insulating film 33 of the sidewall thereof used as amask, an n-type impurity, such as phosphorus, is implanted on thesemiconductor substrate 2. The above-described impurity implantation maybe performed collectively on the element region 10 b, the element region20 b, and the element region 30 b, or may be performed separately on theelement region 10 b, the element region 20 b, and the element region 30b.

At this time, the impurity implantation with respect to thesemiconductor substrate 2 of the element region 10 b is performed underthe conditions that the concentration of the element region 10 b becomeshigher than the LDD region 15 a and LDD region 15 b and that theimpurity is implanted into a deeper region than the LDD region 15 a andLDD region 15 b. Similarly, the impurity implantation with respect tothe semiconductor substrate 2 of the element region 20 b is performedunder the conditions that the concentration of the element region 20 bbecomes higher than the concentration of the LDD region 25 a and LDDregion 25 b and that the impurity is implanted into a deeper region thanthe LDD region 25 a and LDD region 25 b, and the impurity implantationwith respect to the semiconductor substrate 2 of the element region 30 bis performed under the conditions that the concentration of the elementregion 30 b becomes higher than the concentration of the LDD region 35 aand LDD region 35 b and that the impurity is implanted into a deeperregion than the LDD region 35 a and LDD region 35 b. For example,phosphorus is implanted under the conditions: the accelerating energy of8 keV and the dose amount of 1×10¹⁶ cm⁻². Accordingly, the n-typeimpurity region 14 a and impurity region 14 b which function as thesource region or drain region of the memory transistor 10 are formed onthe outside of the n-type LDD region 15 a and LDD region 15 b in thesemiconductor substrate 2 of the element region 10 b. Similarly, then-type impurity region 24 a and impurity region 24 b that function asthe source region or drain region of the logic transistor 20 are formedon the outside of the n-type LDD region 25 a and LDD region 25 b in thesemiconductor substrate 2 of the element region 20 b, and the n-typeimpurity region 34 a and impurity region 34 b that function as thesource region or drain region of the I/O transistor 30 are formed on theoutside of the n-type LDD region 35 a and LDD region 35 b in thesemiconductor substrate 2 of the element region 30 b.

With the above-described manufacturing steps, a semiconductor device 1C(nonvolatile memory), as illustrated in FIG. 13, having the memorytransistor 10, logic transistor 20, and I/O transistor 30 mixedlymounted on the common semiconductor substrate 2 is obtained. Thereafterthe formation of an interlayer insulating film, the formation of a plug,and the formation of an upper wiring layer including the conductors,such as a wiring and a via, and the like are performed.

In the semiconductor device 1C according to the third embodiment, thewidth W1 of the sidewall insulating film 13 of the memory transistor 10is set to be larger than the width W2 of the sidewall insulating film 23of the logic transistor 20 (and the sidewall insulating film 33 of theI/O transistor 30). Accordingly, as described in the above firstembodiment, an improvement in the programming speed of the memorytransistor 10 is achieved. The above-described manufacturing steps makeit possible to manufacture the semiconductor device 1C provided with thememory transistor 10 that exhibits an excellent programming speed.

Note that, although one memory transistor 10 is illustrated here, thesemiconductor device 1C may include a plurality of memory transistors10, or at least one memory transistor 10 and another memory transistor.Moreover, although one logic transistor 20 is illustrated here, thesemiconductor device 1C may include a plurality of logic transistors 20,or at least one logic transistor 20 and another logic transistor.Moreover, although one I/O transistor 30 is illustrated here, thesemiconductor device 1C may include a plurality of I/O transistors 30,or at least one I/O transistor 30 and another I/O transistor.

Next, a fourth embodiment will be described.

Here, as the fourth embodiment, a semiconductor device including thememory transistor 40 described in the above second embodiment andfurther a logic transistor and an I/O transistor will be described.

FIGS. 14 to 25 illustrate an example of the method for manufacturing thesemiconductor device according to the fourth embodiment. Here, FIG. 14is an exemplary cross sectional schematic view of a main portion of thefirst manufacturing step, FIG. 15 is an exemplary cross sectionalschematic view of the main portion of the second manufacturing step,FIG. 16 is an exemplary cross sectional schematic view of the mainportion of the third manufacturing step, FIG. 17 is an exemplary crosssectional schematic view of the main portion of the fourth manufacturingstep, FIG. 18 is an exemplary cross sectional schematic view of the mainportion of the fifth manufacturing step, FIG. 19 is an exemplary crosssectional schematic view of the main portion of the sixth manufacturingstep, FIG. 20 is an exemplary cross sectional schematic view of the mainportion of the seventh manufacturing step, FIG. 21 is an exemplary crosssectional schematic view of the main portion of the eighth manufacturingstep, FIG. 22 is an exemplary cross sectional schematic view of the mainportion of the ninth manufacturing step, FIG. 23 is an exemplary crosssectional schematic view of the main portion of the tenth manufacturingstep, FIG. 24 is an exemplary cross sectional schematic view of the mainportion of the eleventh manufacturing step, and FIG. 25 is an exemplarycross sectional schematic view of the main portion of the twelfthmanufacturing step. Hereinafter, an example of the manufacturing stepsof the semiconductor device according to the fourth embodiment will besequentially described with reference to FIGS. 14 to 25.

First, as illustrated in FIG. 14, a resist pattern 5 c, in which anelement region 40 b of the memory transistor 40 (FIG. 25) is opened andthe element region 20 b of the logic transistor 20 (FIG. 25) and theelement region 30 b of the I/O transistor 30 (FIG. 25) are covered, isformed on the semiconductor substrate 2. With the resist pattern 5 cused as a mask, a predetermined impurity implantation is performed onthe semiconductor substrate 2 of the element region 40 b. With thisimpurity implantation, a well region 6 a and the impurity region 47having a relatively-high concentration to be provided below the channelregion 46 (FIG. 25) of the memory transistor 40 are formed in thesemiconductor substrate 2 of the element region 40 b. The well region 6a and the impurity region 47 are of a p-type, for example, respectively.

This impurity implantation is performed under the following conditions,for example. Boron is implanted under the conditions: the acceleratingenergy of 135 keV or 185 keV and the dose amount of 4×10¹³ cm⁻².Germanium (Ge) is implanted under the conditions: the acceleratingenergy of 30 keV and the dose amount of 5×10¹⁴ cm⁻². Carbon (C) isimplanted under the conditions: the accelerating energy of 5 keV and thedose amount of 5×10¹⁴ cm⁻². Boron is implanted under the conditions: theaccelerating energy of 20 keV and the dose amount of 3×10¹³ cm⁻². Byimplanting each of these impurities under predetermined conditions,respectively, the p-type well region 6 a and the impurity region 47 areformed in the semiconductor substrate 2 of the element region 40 b. Notethat implanting germanium and carbon suppresses the diffusion of thep-type impurity contained in the impurity region 47 into lower and/orupper regions.

After formation of the well region 6 a and the impurity region 47, theresist pattern 5 c is removed, and then a semiconductor material isepitaxially grown on the semiconductor substrate 2. For example, when asilicon substrate is used as the semiconductor substrate 2, silicon thatis the same type of semiconductor material as the semiconductorsubstrate 2 is epitaxially grown with a film thickness of 25 nm on thesemiconductor substrate 2. With the epitaxial growth of thesemiconductor material, a semiconductor layer 8 (non-doped layer) isformed on the impurity region 47 of the element region 40 b asillustrated in FIG. 15. The channel region 46 of the memory transistor40 is formed in the semiconductor layer 8. Note that, although asemiconductor layer similar to the semiconductor layer 8 of the elementregion 40 b is formed also in the element region 20 b and in the elementregion 30 b due to the epitaxial growth, the semiconductor layer isdescribed as the layer integrated into the semiconductor substrate 2 forconvenience here. After formation of the semiconductor layer 8, theelement isolating region 3 is formed which defines the element region 40b, the element region 30 b, and the element region 20 b, as illustratedin FIG. 15.

Next, as illustrated in FIG. 16, a resist pattern 5 d is formed, inwhich the element region 40 b is covered and the element region 20 b andelement region 30 b are opened. With the resist pattern 5 d used as amask, a predetermined impurity implantation is performed on thesemiconductor substrate 2 of the element region 20 b and element region30 b. With this impurity implantation, the well region 6 b is formed inthe semiconductor substrate 2 of the element region 20 b and elementregion 30 b as illustrated in FIG. 16. The well region 6 b is of ap-type, for example. The formation of the well region 6 b is performed,for example, by implanting boron under the conditions: the acceleratingenergy of 135 keV or 185 keV and the dose amount of 4×10¹³ cm⁻² and byimplanting boron fluoride (BF, BF2) under the conditions: theaccelerating energy of 15 keV and the dose amount of 3×10¹² cm⁻².

After formation of the well region 6 b, the resist pattern 5 d isremoved, and as illustrated in FIG. 17, a resist pattern 5 e is newlyformed, in which the element region 30 b and element region 40 b arecovered and the element region 20 b is opened. With the resist pattern 5e used as a mask, impurity implantation for adjusting the thresholdvoltage of the logic transistor 20 is performed on the semiconductorsubstrate 2 of the element region 20 b. This impurity implantation isperformed, for example, by implanting boron fluoride under theconditions: the accelerating energy of 15 keV and the dose amount of1×10¹³ mm⁻². Accordingly, the channel region 26 of the logic transistor20 is formed as illustrated in FIG. 17.

Subsequently, the resist pattern 5 e is removed, and an oxide film 7 isformed, for example, with a film thickness of 7 nm using thermaloxidation on the semiconductor substrate 2 of the element region 20 b,element region 30 b, and element region 40 b, respectively, asillustrated in FIG. 18. Then, a resist pattern 5 f is newly formed, inwhich the element region 20 b is opened, and then the oxide film 7formed on the semiconductor substrate 2 of the element region 20 b isremoved.

Next, the resist pattern 5 f is removed, and an oxide film is formed,for example, with a film thickness of 1.8 nm on the semiconductorsubstrate 2 using thermal oxidation again. Accordingly, the gateinsulating film 21, gate insulating film 31, and gate insulating film 41each having a predetermined film thickness are formed in the elementregion 20 b of the logic transistor 20, in the element region 30 b ofthe I/O transistor 30, and in the element region 40 b of the memorytransistor 40, respectively, as illustrated in FIG. 19.

After formation of the gate insulating film 21, gate insulating film 31,and gate insulating film 41, the polysilicon 4 that is a gate electrodematerial is formed, for example, with a film thickness of 100 nm asillustrated in FIG. 20, and then the patterning of the polysilicon 4 isperformed. Thus, the gate electrode 22 of the logic transistor 20, thegate electrode 32 of the I/O transistor 30, and the gate electrode 42 ofthe memory transistor 40 are formed.

After formation of the gate electrode 22, gate electrode 32, and gateelectrode 42, a resist pattern 5 g is formed, in which the elementregion 40 b is opened, as illustrated in FIG. 21, and then with theresist pattern 5 g used as a mask, impurity implantation is performed onthe semiconductor substrate 2 of the element region 40 b. With thisimpurity implantation, the LDD region 45 a and LDD region 45 b areformed in the semiconductor substrate 2 on both sides of the gateelectrode 42, as illustrated in FIG. 21. The LDD region 45 a and LDDregion 45 b are formed, for example, by implanting arsenic that is ann-type impurity under the conditions: the accelerating energy of 10 keVand the dose amount of 1×10¹³ cm⁻². The channel region 46 of the memorytransistor 40 is formed between the LDD region 45 a and LDD region 45 babove the previously formed relatively-high concentration impurityregion 47.

Similarly, a resist pattern 5 h is formed, in which the element region30 b is opened, as illustrated in FIG. 22, and then with the resistpattern 5 h used as a mask, impurity implantation is performed on thesemiconductor substrate 2 of the element region 30 b to form the LDDregion 35 a and LDD region 35 b of the I/O transistor 30. Moreover, asillustrated in FIG. 23, a resist pattern 5 i is formed, in which theelement region 20 b is opened, and then with the resist pattern 5 i usedas a mask, impurity implantation is performed on the semiconductorsubstrate 2 of the element region 20 b to form the LDD region 25 a andLDD region 25 b of the logic transistor 20. The LDD region 35 a and LDDregion 35 b of the I/O transistor 30 illustrated in FIG. 22 are formedby implanting, for example, phosphorus that is an n-type impurity underthe conditions: the accelerating energy of 35 keV and the dose amount of3×10¹³ cm⁻². The LDD region 25 a and LDD region 25 b of the logictransistor 20 illustrated in FIG. 23 are formed by implanting, forexample, arsenic that is an n-type impurity under the conditions: theaccelerating energy of 1.5 keV and the dose amount of 1×10¹⁵ cm⁻². Thechannel region 36 of the I/O transistor 30 is formed between the LDDregion 35 a and the LDD region 35 b, while the channel region 26 of thelogic transistor 20 is formed between the LDD region 25 a and the LDDregion 25 b.

Note that the sequence of the steps illustrated in FIGS. 21 to 23 may beinterchanged with each other and performed.

Next, an insulating film, e.g., a silicon oxide film or a siliconnitride film, or a stacked film thereof is formed with a film thicknessof 80 nm, which is then etched back. Accordingly, as illustrated in FIG.24, the sidewall insulating film 23, sidewall insulating film 33, andsidewall insulating film 43 are formed on the respective sidewalls ofthe gate electrode 22, gate electrode 32, and gate electrode 42.

Note that, when only the sidewall insulating film 43 is formed in astacked structure of an oxide film of silicon oxide or the like and anitride film of silicon nitride or the like, the following steps may beperformed after formation of the gate insulating film 21, gateinsulating film 31, and gate insulating film 41 as in the above FIG. 19.

That is, after the step of the above FIG. 19, the polysilicon 4 is firstformed on the gate insulating film 21, gate insulating film 31, and gateinsulating film 41. Next, in accordance with the example of the step ofthe above FIG. 9 described in the third embodiment, the gate electrode42 (element corresponding to the gate electrode 12 of FIG. 9) is formedin the element region 40 b of the memory transistor 40. Next, inaccordance with the example of the step of FIG. 10 (or FIG. 21), the LDDregion 45 a and LDD region 45 b (elements corresponding to the LDDregion 15 a and LDD region 15 b of FIG. 10) are formed in the elementregion 40 b of the memory transistor 40. Next, in accordance with theexample of the step of FIG. 11, an oxide film and nitride film (elementscorresponding to the oxide film 13 a and nitride film 13 b of FIG. 11)are stacked and formed with a predetermined film thickness, and are thenetched back to form the sidewall insulating film 43 (elementcorresponding to the sidewall insulating film 13 of FIG. 11) of thestacked structure of the oxide film and nitride film. Next, inaccordance with the example of the step of FIG. 12, the polysilicon 4 ofthe element region 30 b and element region 20 b is patterned to form thegate electrode 32 and gate electrode 22.

Subsequently, in accordance with the example of the steps of FIGS. 22and 23 described in the fourth embodiment, the LDD region 35 a and LDDregion 35 b and the LDD region 25 a and LDD region 25 b are formed inthe element region 30 b and in the element region 20 b, respectively.Then, a single layer of silicon oxide film is formed with apredetermined film thickness as the insulating film, and is then etchedback to form the sidewall insulating film 33 and sidewall insulatingfilm 23 each having a single-layer structure in the element region 30 band in the element region 20 b, respectively.

Accordingly, it is possible to form the sidewall insulating film 43 ofthe element region 40 b in a stacked structure of an oxide film and anitride film, form the sidewall insulating film 33 of the element region30 b and the sidewall insulating film 23 of the element region 20 b in asingle-layer structure, respectively, and obtain a structure as in FIG.24. This facilitates the accumulation of charges in the sidewallinsulating film 43, and also makes it possible to suppress theaccumulation of charges into the sidewall insulating film 33 andsidewall insulating film 23, thereby minimizing the degradation of theperformance of the I/O transistor 30 and logic transistor 20.

The steps may be changed as needed in accordance with the structureadopted for the sidewall insulating film 33, sidewall insulating film43, and sidewall insulating film 23.

After performing the steps up to the step of FIG. 24 in theabove-described manner, the process proceeds to the step of FIG. 25.Here, first, with the gate electrode 22 and the sidewall insulating film23 of the side wall thereof, the gate electrode 32 and the sidewallinsulating film 33 of the side wall thereof, and the gate electrode 42and the sidewall insulating film 43 of the side wall thereof used as amask, an n-type impurity, such as phosphorus, is implanted with respectto the semiconductor substrate 2. Such impurity implantation isperformed by implanting phosphorus under the conditions: theaccelerating energy of 8 keV and the dose amount of 1×10¹⁶ cm⁻².Accordingly, as illustrated in FIG. 25, the n-type impurity region 24 aand impurity region 24 b which function as the source region or drainregion of the logic transistor 20 are formed on the outside of then-type LDD region 25 a and LDD region 25 b in the semiconductorsubstrate 2 of the element region 20 b. Similarly, as illustrated inFIG. 25, the n-type impurity region 34 a and impurity region 34 b whichfunction as the source region or drain region of the I/O transistor 30are formed on the outside of the n-type LDD region 35 a and LDD region35 b in the semiconductor substrate 2 of the element region 30 b. Asillustrated in FIG. 25, the n-type impurity region 44 a and impurityregion 44 b which function as the source region or drain region of thememory transistor 40 are formed on the outside of the n-type LDD region45 a and LDD region 45 b in the semiconductor substrate 2 of the elementregion 40 b.

With the above-described steps, a semiconductor device 1D (nonvolatilememory), as illustrated in FIG. 25, having the logic transistor 20, I/Otransistor 30, and memory transistor 40 mixedly mounted on the commonsemiconductor substrate 2 is obtained. Thereafter, the formation of aninterlayer insulating film, the formation of a plug, and the formationof an upper wiring layer including the conductors, such as a wiring anda via, and the like are performed.

In the semiconductor device 1D according to the fourth embodiment, thechannel region 46 having a lower impurity concentration is provided inthe memory transistor 40, and the impurity region 47 having arelatively-high concentration is provided below the channel region 46.Accordingly, as described in the second embodiment, an improvement inthe programming speed of the memory transistor 40 is achieved. Theabove-described steps make it possible to manufacture the semiconductordevice 1D provided with the memory transistor 40 that exhibits anexcellent programming speed.

Note that, although one memory transistor 40 is illustrated here, thesemiconductor device 1D may include a plurality of memory transistors40, or at least one memory transistor 40 and another memory transistor.Moreover, although one logic transistor 20 is illustrated here, thesemiconductor device 1D may include a plurality of logic transistors 20,or at least one logic transistor 20 and another logic transistor.Moreover, although one I/O transistor 30 is illustrated here, thesemiconductor device 1D may include a plurality of I/O transistors 30,or at least one I/O transistor 30 and another I/O transistor.

Next, a fifth embodiment will be described.

Here, as the fifth embodiment, a semiconductor device is described, inwhich a channel structure having a region with a high impurityconcentration provided below a channel region with a low impurityconcentration as described above is adopted for both a memory transistorand a logic transistor mixedly mounted with the memory transistor.

FIGS. 26 to 31 illustrate an example of the method for manufacturing thesemiconductor device according to the fifth embodiment. Here, FIG. 26 isan exemplary cross sectional schematic view of a main portion of thefirst manufacturing step, FIG. 27 is an exemplary cross sectionalschematic view of the main portion of the second manufacturing step,FIG. 28 is an exemplary cross sectional schematic view of a main portionof the third manufacturing step, FIG. 29 is an exemplary cross sectionalschematic view of a main portion of the fourth manufacturing step, FIG.30 is an exemplary cross sectional schematic view of a main portion ofthe fifth manufacturing step, and FIG. 31 is an exemplary crosssectional schematic view of a main portion of the sixth manufacturingstep. Hereinafter, an example of the manufacturing steps of thesemiconductor device according to the fifth embodiment will besequentially described with reference to FIGS. 26 to 31.

First, as illustrated in FIG. 26, a resist pattern 5 j, in which theelement region 40 b of the memory transistor 40 (FIG. 31) and theelement region 50 b of the logic transistor 50 (FIG. 31) are opened andthe element region 30 b of the I/O transistor 30 (FIG. 31) is covered,is formed on the semiconductor substrate 2. With the resist pattern 5 jused as a mask, a predetermined impurity implantation is performed onthe semiconductor substrate 2 of the element region 40 b and elementregion 50 b. With this impurity implantation, the well region 6 a, theimpurity region 47 having a relatively-high concentration of the memorytransistor 40, and the impurity region 57 having a relatively-highconcentration of the logic transistor 50 are formed. The well region 6a, the impurity region 47, and the impurity region 57 each are of ap-type, for example.

The above-described impurity implantation is performed under thefollowing conditions, for example.

Boron is implanted under the conditions: the accelerating energy of 135keV or 185 keV and the dose amount of 4×10¹³ cm⁻². Germanium isimplanted under the conditions: the accelerating energy of 30 keV andthe dose amount of 5×10¹⁴ cm⁻². Carbon is implanted under theconditions: the accelerating energy of 5 keV and the dose amount of5×10¹⁴ cm⁻². Boron is implanted under the conditions: the acceleratingenergy of 20 keV and the dose amount of 5×10¹² cm⁻². Boron fluoride isimplanted under the conditions: the accelerating energy of 10 keV andthe dose amount of 1.5×10¹² cm⁻². By implanting each of these impuritiesunder the predetermined conditions, respectively, the p-type well region6 a and the impurity region 47 are formed in the semiconductor substrate2 of the element region 40 b, and the p-type well region 6 a and theimpurity region 57 are formed in the semiconductor substrate 2 of theelement region 50 b. Note that implanting germanium and carbonsuppresses the diffusion of the p-type impurities contained in theimpurity region 47 and impurity region 57 into lower and/or upperregions.

When the logic transistor 50 to form is a super-low leakage transistor,the concentration of the impurity region 57 is set to be low as comparedwith the optimum concentration of the impurity region 47 of the memorytransistor 40 in order to minimize a junction leak current.

Therefore, when the logic transistor 50 is formed as an ultra-lowleakage transistor, impurity implantation with respect to thesemiconductor substrate 2 of the element region 50 b is performed undersuch conditions as to obtain the impurity region 57 having aconcentration optimum for the logic transistor 50, in the stepillustrated in FIG. 26. Further, as illustrated in FIG. 27, additionalimpurity implantation is performed on the semiconductor substrate 2 ofthe element region 40 b of the memory transistor 40 to obtain theimpurity region 47 having a concentration optimum for the memorytransistor 40. The additional impurity implantation is performed, asillustrated in FIG. 27, with a resist pattern 5 k, in which the elementregion 40 b is opened, used as a mask, by implanting, for example, boronunder the conditions: the accelerating energy of 20 keV and the doseamount of 2.5×10¹³ mm⁻².

Thereafter, a semiconductor material is epitaxially grown on thesemiconductor substrate 2 to form a semiconductor layer 8 a (non-dopedlayer) on the impurity region 47 of the element region 40 b and on theimpurity region 57 of the element region 50 b as illustrated in FIG. 28.The channel region 46 of the memory transistor 40 and the channel region56 of the logic transistor 50 are formed in the semiconductor layer 8 a.Note that, although a semiconductor layer similar to the semiconductorlayer 8 a of the element region 40 b and element region 50 b is formedalso in the element region 30 b due to the epitaxial growth, the formersemiconductor layer is described as the layer integrated into thesemiconductor substrate 2 for convenience here. After formation of thesemiconductor layer 8 a, the element isolating region 3 is formed whichdefines the element region 40 b, the element region 30 b, and theelement region 50 b, as illustrated in FIG. 28.

Next, as illustrated in FIG. 29, with a resist pattern 5 m, in which theelement region 30 b is opened, used as a mask, impurity implantation isperformed to form the well region 6 b in the semiconductor substrate 2of the element region 30 b. The well region 6 b is of a p-type, forexample. Subsequently, impurity implantation for adjusting the thresholdvoltage of the I/O transistor 30 may be performed on the semiconductorsubstrate 2 of the element region 30 b.

Thereafter, the steps similar to the steps in FIGS. 18 to 25 describedin the above fourth embodiment are performed to obtain a structureillustrated in FIG. 30 and a structure as illustrated in FIG. 31.

That is, first in accordance with the example of steps of FIGS. 18 and19, the gate insulating film 31, gate insulating film 41, and gateinsulating film 51 each having a predetermined film thickness are formedin the element region 30 b, in the element region 40 b, and in theelement region 50 b, respectively, by thermal oxidation. Next, inaccordance with the example of step of FIG. 20, the gate electrode 32,gate electrode 42, and gate electrode 52 are formed by forming andpatterning polysilicon. Then, in accordance with the example of steps ofFIGS. 21 to 23, the LDD region 45 a and LDD region 45 b, the LDD region35 a and LDD region 35 b, and the LDD region 55 a and LDD region 55 bare formed by implanting an impurity under the predetermined conditions,respectively. The LDD region 45 a and LDD region 45 b, the LDD region 35a and LDD region 35 b, and the LDD region 55 a and LDD region 55 b eachare of an n-type, for example. Accordingly, the structure as illustratedin FIG. 30 is obtained. The channel region 36 of the I/O transistor 30is formed between the LDD region 35 a and LDD region 35 b. The channelregion 46 of the memory transistor 40 is formed between the LDD region45 a and LDD region 45 b. The channel region 56 of the logic transistor50 is formed between the LDD region 55 a and the LDD region 55 b.

Furthermore, by forming and etching back an insulating film inaccordance with the example of step of FIG. 24, the sidewall insulatingfilm 33, sidewall insulating film 43, and sidewall insulating film 53are formed on the respective sidewalls of the gate electrode 32, gateelectrode 42, and gate electrode 52. Then, in accordance with theexample of step of FIG. 25, an impurity region that functions as thesource region or drain region of the I/O transistor 30, memorytransistor 40, and logic transistor 50 is formed by implanting animpurity under the predetermined conditions. That is, the n-typeimpurity region 34 a and impurity region 34 b which function as thesource region or drain region of the I/O transistor 30 are formed on theoutside of the n-type LDD region 35 a and LDD region 35 b in thesemiconductor substrate 2 of the element region 30 b. Similarly, then-type impurity region 44 a and impurity region 44 b which function asthe source region or drain region of the memory transistor 40 are formedon the outside of the n-type LDD region 45 a and LDD region 45 b in thesemiconductor substrate 2 of the element region 40 b. The n-typeimpurity region 54 a and impurity region 54 b which function as thesource region or drain region of the logic transistor 50 are formed onthe outside of the n-type LDD region 55 a and LDD region 55 b in thesemiconductor substrate 2 of the element region 50 b. Accordingly, thestructure as illustrated in FIG. 31 is obtained.

Note that, the sidewall insulating film 33, sidewall insulating film 43,and sidewall insulating film 53 may each have a single-layer structureof an oxide film or a nitride film, or a stacked structure of an oxidefilm and a nitride film. As described in the above fourth embodiment,the steps may be changed as needed in accordance with a structureadopted for the sidewall insulating film 33, sidewall insulating film43, and sidewall insulating film 53.

With the above-described steps, a semiconductor device 1E (nonvolatilememory) having the I/O transistor 30, memory transistor 40, and logictransistor 50 mixedly mounted on the common semiconductor substrate 2 isobtained. Thereafter, the formation of an interlayer insulating film,the formation of a plug, and the formation of an upper wiring layerincluding the conductors, such as a wiring and a via, and the like areperformed.

In the semiconductor device 1E according to the fifth embodiment, thechannel region 46 having a lower impurity concentration is provided inthe memory transistor 40 and the impurity region 47 having arelatively-high concentration is provided below the channel region 46.Accordingly, as described in the above second embodiment, an improvementin the programming speed of the memory transistor 40 is achieved.Furthermore, in the semiconductor device 1E according to the fifthembodiment, the channel region 56 having a lower impurity concentrationis provided also in the logic transistor 50, and the impurity region 57having a relatively-high concentration is provided below the channelregion 56. Accordingly, a reduction of the variation of the thresholdvoltage, a reduction of the power consumption, and the like of the logictransistor 50 are achieved. The above-described steps make it possibleto manufacture the semiconductor device 1E provided with the memorytransistor 40 that exhibits an excellent programming speed and the logictransistor 50 that exhibits an excellent operation performance.

Note that, here, a case is illustrated, where the logic transistor 50having an ultra-low leakage is assumed, and impurity implantation isfirstly performed under such conditions as to obtain the impurity region57 having a concentration optimum for the logic transistor 50 (FIG. 26),and then an additional impurity implantation is performed to obtain theimpurity region 47 having a concentration optimum for the memorytransistor 40 (FIG. 27).

On the other hand, when the constraint on the power consumption of thewhole semiconductor device 1E is relaxed, the constraint on the leakagecurrent of the logic transistor 50 is also relaxed. In this case, theimpurity region 57 of the logic transistor 50 may be made to have ahigher impurity concentration. As the conditions for the impurityimplantation in this case, the following may be adopted. Boron isimplanted under the conditions: the accelerating energy of 135 keV or185 keV and the dose amount of 4×10¹³ cm⁻². Germanium is implanted underthe conditions: the accelerating energy of 30 keV and the dose amount of5×10¹⁴ cm⁻². Carbon is implanted under the conditions: the acceleratingenergy of 5 keV and the dose amount of 5×10¹⁴ cm⁻². Boron is implantedunder the conditions: the accelerating energy of 20 keV and the doseamount of 1.8×10¹³ cm⁻². Boron fluoride is implanted under theconditions: the accelerating energy of 25 keV and the dose amount of6×10¹² cm⁻². Boron fluoride is implanted under the conditions: theaccelerating energy of 10 keV and the dose amount of 3.0×10¹² cm⁻². Inthe step of FIG. 26, the p-type well region 6 a, impurity region 47, andimpurity region 57 are formed in the semiconductor substrate 2 byimplanting each impurity under such conditions. Thereafter, the step ofFIG. 28 and the subsequent steps may be performed without going throughthe step of FIG. 27. When such an approach is adopted, the thresholdvoltage of the memory transistor 40 becomes slightly high as comparedwith the above-described approach (FIGS. 26 and 27) in which anadditional impurity implantation is performed to obtain the impurityregion 47. However, because the constraint on the power consumption ofthe whole semiconductor device 1E is relaxed, it is possible to copewith such a problem by increasing the read voltage of the memorytransistor 40.

Moreover, when the constraint on the leakage current is relaxed and theimpurity region 57 of the logic transistor 50 may be made to have ahigher impurity concentration, the following approach may be used. Thatis, in the step of FIG. 26, impurity implantation is simultaneouslyperformed on the semiconductor substrate 2 of the element region 40 band element region 50 b under such conditions as to obtain the impurityregion 47 having a concentration optimum for the memory transistor 40.Accordingly, the impurity region 47 having a concentration optimum forthe memory transistor 40 is formed in the semiconductor substrate 2 ofthe element region 40 b, and the impurity region 57 having aconcentration equal to that of the impurity region 47 is formed in thesemiconductor substrate 2 of the element region 50 b of the logictransistor 50. Thereafter, the step of FIG. 28 and the subsequent stepsmay be performed without going through the step of FIG. 27. When theconstraint on the leakage current of the logic transistor 50 is relaxed,such an approach may be used.

Moreover, when the constraint on the leakage current is relaxed and theimpurity region 57 of the logic transistor 50 may be made to have ahigher impurity concentration, the following approach may be used. Thatis, in the step of FIG. 26, impurity implantation is performed undersuch conditions as to obtain an impurity region having a concentrationhigher than the concentration optimum for the logic transistor 50 of theultra-low leakage and also to obtain an impurity region having aconcentration lower than the concentration optimum for the memorytransistor 40. Under such conditions, impurity implantation issimultaneously performed on the semiconductor substrate 2 of the elementregion 40 b and the element region 50 b to form the impurity region 47having a lower concentration and the impurity region 57 having a higherconcentration as compared with the above-described approach (FIGS. 26and 27). Thereafter, the step of FIG. 28 and the subsequent steps may beperformed without going through the step of FIG. 27. When the constrainton the leakage current of the logic transistor 50 is relaxed, such anapproach may be used.

In either of the approaches described about the impurity region 47 andimpurity region 57, the step of an additional impurity implantation asillustrated in FIG. 27 may be omitted to reduce the manufacturing stepsof the semiconductor device 1E.

Note that, although one memory transistor 40 is illustrated here, thesemiconductor device 1E may include a plurality of memory transistors40, or at least one memory transistor 40 and another memory transistor.Moreover, although one logic transistor 50 is illustrated here, thesemiconductor device 1E may include a plurality of logic transistors 50,or at least one logic transistor 50 and another logic transistor.Moreover, although one I/O transistor 30 is illustrated here, thesemiconductor device 1E may include a plurality of I/O transistors 30,or at least one I/O transistor 30 and another I/O transistor.

Next, a sixth embodiment will be described.

FIG. 32 illustrates a first configuration example of a semiconductordevice according to the sixth embodiment. FIG. 32 schematicallyillustrates the cross section of a main portion of the firstconfiguration example of the semiconductor device.

A semiconductor device 1Fa illustrated in FIG. 32 differs from thesemiconductor device 1D (FIG. 25) described in the above fourthembodiment in that it includes the memory transistor 40 having thesidewall insulating film 43 with the width W1 larger than the width W2of the sidewall insulating film 23 of the logic transistor 20. Note thatthe sidewall insulating film 43 having a stacked structure of the oxidefilm 43 a and nitride film 43 b is illustrated in FIG. 32.

The semiconductor device 1Fa as illustrated in FIG. 32 may be obtained,for example, by forming each element in accordance with the example ofsteps of FIGS. 8 to 13 described in the above third embodiment afterperforming the steps of FIGS. 14 to 17 described in the above fourthembodiment.

That is, the steps of FIGS. 14 to 17 are first performed to obtain thesemiconductor substrate 2, as in the above FIG. 17, including theelement region 40 b of the memory transistor 40, the element region 30 bof the I/O transistor 30, and the element region 20 b of the logictransistor 20, each element region being defined by the elementisolating region 3. The element region 40 b of the memory transistor 40includes the well region 6 a, the impurity region 47, and the channelregion 46 (semiconductor layer 8). The element region 30 b of the I/Otransistor 30 includes the well region 6 b. The element region 20 b ofthe logic transistor 20 includes the well region 6 b and the channelregion 26. The well region 6 a, the well region 6 b, and the impurityregion 47 each are of a p-type, for example.

Subsequently, in accordance with the example of FIG. 8, the gateinsulating film 41 (element corresponding to the gate insulating film 11of FIG. 8), gate insulating film 31, and gate insulating film 21 eachhaving a predetermined film thickness are formed in the element region40 b, the element region 30 b, and the element region 20 b,respectively, and then the polysilicon 4 is formed on these gateinsulating films.

Next, in accordance with the example of FIG. 9, the polysilicon 4 ispatterned to form the gate electrode 42 (element corresponding to thegate electrode 12 of FIG. 9) of the memory transistor 40.

Next, in accordance with the example of FIG. 10, the LDD region 45 a andLDD region 45 b of the memory transistor 40 (elements corresponding tothe LDD region 15 a and LDD region 15 b of FIG. 10) are formed byimpurity implantation. The LDD region 45 a and LDD region 45 b are of ann-type, for example.

Next, in accordance with the example of FIG. 11, the oxide film 43 a andthe nitride film 43 b (elements corresponding to the oxide film 13 a andthe nitride film 13 b of FIG. 11) are formed and etched back.Accordingly, the sidewall insulating film 43 (element corresponding tothe sidewall insulating film 13 of FIG. 11) of the memory transistor 40having the predetermined width W1 is formed.

Next, in accordance with the example of FIG. 12, the polysilicon 4 ofthe element region 30 b and element region 20 b is patterned to form thegate electrode 32 of the I/O transistor 30 and the gate electrode 22 ofthe logic transistor 20.

Next, in accordance with the example of FIG. 13, the LDD region 35 a andLDD region 35 b are formed in the semiconductor substrate 2 of theelement region 30 b, and the LDD region 25 a and LDD region 25 b areformed in the semiconductor substrate 2 of the element region 20 b. TheLDD region 35 a and LDD region 35 b and the LDD region 25 a and LDDregion 25 b each are of an n-type, for example. Furthermore, thesidewall insulating film 33 and sidewall insulating film 23 are formedon the side wall of the gate electrode 32 of the element region 30 b andon the side wall of the gate electrode 22 of the element region 20 b,respectively, by forming and etching back an insulating film. Then, theimpurity region 44 a and impurity region 44 b (elements corresponding tothe impurity region 14 a and impurity region 14 b of FIG. 13) whichfunction as the source region or drain region of the memory transistor40 are formed in the element region 40 b by impurity implantation.Similarly, the impurity region 34 a and impurity region 34 b whichfunction as the source region or drain region of the I/O transistor 30are formed in the element region 30 b by impurity implantation, and theimpurity region 24 a and impurity region 24 b which function as thesource region or drain region of the logic transistor 20 are formed inthe element region 20 b. The impurity region 44 a and impurity region 44b, the impurity region 34 a and impurity region 34 b, and the impurityregion 24 a and impurity region 24 b each are of an n-type, for example.

With such steps, the semiconductor device 1Fa (nonvolatile memory) asillustrated in FIG. 32 is obtained. Thereafter, the formation of aninterlayer insulating film, the formation of a plug, and the formationof an upper wiring layer including the conductors, such as a wiring anda via, and the like are performed.

In the semiconductor device 1Fa of the first configuration exampleaccording to the sixth embodiment, the channel region 46 having a lowerimpurity concentration is provided in the memory transistor 40, and theimpurity region 47 having a relatively-high concentration is providedbelow the channel region 46. Furthermore, the width W1 of the sidewallinsulating film 43 of the logic transistor 40 is set to be larger thanthe width W2 of the sidewall insulating film 23 of the logic transistor20 (and the sidewall insulating film 33 of the I/O transistor 30). Theseconfigurations contribute to an improvement in the programming speed ofthe memory transistor 40, as described in the above first and secondembodiments. Adoption of these configurations makes it possible torealize the semiconductor device 1Fa provided with the memory transistor40 exhibiting an excellent programming speed.

Note that, although one memory transistor 40 is illustrated here, thesemiconductor device 1Fa may include a plurality of memory transistors40, or at least one memory transistor 40 and another memory transistor.Moreover, although one logic transistor 20 is illustrated here, thesemiconductor device 1Fa may include a plurality of logic transistors20, or at least one logic transistor 20 and another logic transistor.Moreover, although one I/O transistor 30 is illustrated here, thesemiconductor device 1Fa may include a plurality of I/O transistors 30,or at least one I/O transistor 30 and another I/O transistor.

FIG. 33 illustrates a second configuration example of the semiconductordevice according to the sixth embodiment. FIG. 33 schematicallyillustrates the cross section of a main portion of the secondconfiguration example of the semiconductor device.

A semiconductor device 1Fb illustrated in FIG. 33 differs from thesemiconductor device 1E (FIG. 31) described in the above fifthembodiment in that it includes the memory transistor 40 having thesidewall insulating film 43 with the width W1 larger than the width W2of the sidewall insulating film 53 of the logic transistor 50. Note thatthe sidewall insulating film 43 having a stacked structure of the oxidefilm 43 a and nitride film 43 b is illustrated in FIG. 33.

The semiconductor device 1Fb as illustrated in FIG. 33 may be obtained,for example, by forming each element in accordance with the example ofsteps of FIGS. 8 to 13 described in the above third embodiment afterperforming the steps of FIGS. 26 to 29 described in the above fifthembodiment.

That is, the steps of FIGS. 26 to 29 are first performed to obtain thesemiconductor substrate 2, as illustrated in FIG. 29, including theelement region 40 b of the memory transistor 40, the element region 30 bof the I/O transistor 30, and the element region 50 b of the logictransistor 50, each element region being defined by the elementisolating region 3. The element region 40 b of the memory transistor 40includes the well region 6 a, the impurity region 47, and the channelregion 46 (semiconductor layer 8 a). The element region 30 b of the I/Otransistor 30 includes the well region 6 b. The element region 20 b ofthe logic transistor 20 includes the well region 6 a, the impurityregion 57, and the channel region 56 (semiconductor layer 8 a). The wellregion 6 a, the well region 6 b, the impurity region 47, and theimpurity region 57 each are of a p-type, for example.

Subsequently, the gate insulating film 41 (element corresponding to thegate insulating film 11 of FIG. 8), gate insulating film 31, and gateinsulating film 51 (element corresponding to the gate insulating film 21of FIG. 8) each having a predetermined film thickness are formed in theelement region 40 b, the element region 30 b, and the element region 50b, respectively, in accordance with the example of FIG. 8. Furthermore,the polysilicon 4 is formed on these gate insulating films.

Next, in accordance with the example of FIG. 9, the polysilicon 4 ispatterned to form the gate electrode 42 (element corresponding to thegate electrode 12 of FIG. 9) of the memory transistor 40.

Next, in accordance with the example of FIG. 10, the LDD region 45 a andLDD region 45 b (elements corresponding to the LDD region 15 a and LDDregion 15 b of FIG. 10) of the memory transistor 40 are formed byimpurity implantation. The LDD region 45 a and LDD region 45 b are of ann-type, for example.

Next, in accordance with the example of FIG. 11, the oxide film 43 a andthe nitride film 43 b (elements corresponding to the oxide film 13 a andthe nitride film 13 b of FIG. 11) are formed and etched back.Accordingly, the sidewall insulating film 43 (element corresponding tothe sidewall insulating film 13 of FIG. 11) of the memory transistor 40having the predetermined width W1 is formed.

Next, in accordance with the example of FIG. 12, the polysilicon 4 ofthe element region 30 b and element region 20 b is patterned to form thegate electrode 32 of the I/O transistor 30 and the gate electrode 52(element corresponding to the gate electrode 22 of FIG. 12) of the logictransistor 50.

Next, in accordance with the example of FIG. 13, the LDD region 35 a andLDD region 35 b are formed in the semiconductor substrate 2 of theelement region 30 b, and the LDD region 55 a and the LDD region 55 b(elements corresponding to the LDD region 25 a and the LDD region 25 bof FIG. 13) are formed in the semiconductor substrate 2 of the elementregion 50 b. The LDD region 35 a and LDD region 35 b and the LDD region55 a and LDD region 55 b each are of an n-type, for example.Furthermore, the sidewall insulating film 33 and sidewall insulatingfilm 53 (element corresponding to the sidewall insulating film 23 ofFIG. 13) are formed on the side wall of the gate electrode 32 of theelement region 30 b and on the side wall of the gate electrode 52 of theelement region 50 b, respectively, by forming and etching back aninsulating film. Then, the impurity region 44 a and impurity region 44 b(elements corresponding to the impurity region 14 a and impurity region14 b of FIG. 13) which function as the source region or drain region ofthe memory transistor 40 are formed in the element region 40 b byimpurity implantation. Similarly, by impurity implantation, the impurityregion 34 a and impurity region 34 b which function as the source regionor drain region of the I/O transistor 30 are formed in the elementregion 30 b. The impurity region 54 a and impurity region 54 b (elementscorresponding to the impurity region 24 a and impurity region 24 b ofFIG. 13) which function as the source region or drain region of thelogic transistor 50 are formed in the element region 50 b. The impurityregion 44 a and impurity region 44 b, the impurity region 34 a andimpurity region 34 b, and the impurity region 54 a and impurity region54 b each are of an n-type, for example.

With these steps, the semiconductor device 1Fb (nonvolatile memory) asillustrated in FIG. 33 is obtained. Thereafter, the formation of aninterlayer insulating film, the formation of a plug, and the formationof an upper wiring layer including the conductors, such as a wiring anda via, and the like are performed.

In the semiconductor device 1Fb of the second configuration exampleaccording to the sixth embodiment, the channel region 46 having a lowerimpurity concentration is provided in the memory transistor 40, and theimpurity region 47 having a relatively-high concentration is providedbelow the channel region 46. Furthermore, the width W1 of the sidewallinsulating film 43 of the memory transistor 40 is set to be larger thanthe width W2 of the sidewall insulating film 23 of the logic transistor20 (and the sidewall insulating film 33 of the I/O transistor 30). Theseconfigurations contribute to an improvement in the programming speed ofthe memory transistor 40, as described in the above first and secondembodiments. Moreover, also in the logic transistor 50 as with thememory transistor 40, the channel region 56 having a lower impurityconcentration is provided, and the impurity region 57 having arelatively-high concentration is provided below the channel region 56,thereby achieving a reduction of the variation of the threshold voltage,a reduction of the power consumption, and the like. Adoption of theseconfigurations makes it possible to realize the semiconductor device 1Fbprovided with the memory transistor 40 exhibiting an excellentprogramming speed and the logic transistor 50 exhibiting an excellentoperational performance.

Note that, although one memory transistor 40 is illustrated here, thesemiconductor device 1Fb may include a plurality of memory transistors40, or at least one memory transistor 40 and another memory transistor.Moreover, although one logic transistor 50 is illustrated here, thesemiconductor device 1Fb may include a plurality of logic transistors50, or at least one logic transistor 50 and another logic transistor.Moreover, although one I/O transistor 30 is illustrated here, thesemiconductor device 1Fb may include a plurality of I/O transistors 30,or at least one I/O transistor 30 and another I/O transistor.

Next, a seventh embodiment will be described.

For example, in order to increase the generation of hot carriers in thememory transistor 40 provided with the impurity region 47 having arelatively-high concentration below the channel region 46 having a lowerimpurity concentration, the following approach may be adopted: i.e., anapproach for making steeper the concentration distribution of theimpurity region 44 a and impurity region 44 b which function as thesource region or drain region of the memory transistor 40. In order tomake steeper the concentration distribution of the impurity region 44 aand impurity region 44 b of the memory transistor 40, the steps asillustrated in FIGS. 34 and 35 are performed, for example.

FIGS. 34 and 35 illustrate an example of the method for manufacturing asemiconductor device according to the seventh embodiment. Here, FIG. 34is an exemplary cross sectional schematic view of a main portion of thefirst manufacturing step, while FIG. 35 is an exemplary cross sectionalschematic view of the main portion of the second manufacturing step.Hereinafter, an example of the manufacturing steps of the semiconductordevice according to the seventh embodiment will be sequentiallydescribed with reference to FIGS. 34 and 35.

Here, a case is taken as an example, where the concentrationdistribution of the impurity region 44 a and impurity region 44 b of thememory transistor 40 of the semiconductor device 1Fb (FIG. 33) taken asthe second configuration example in the above sixth embodiment is madesteeper. In this case, impurity implantation with respect to the elementregion 40 b of the memory transistor 40 and impurity implantation withrespect to the element region 30 b of the I/O transistor 30 and withrespect to the element region 50 b of the logic transistor 50 areperformed in separate steps, not simultaneously (collectively).

For example, after formation of the sidewall insulating film 33,sidewall insulating film 43, and sidewall insulating film 53, a resistpattern 5 p that covers the element region 40 b of the memory transistor40 is formed first as illustrated in FIG. 34. With the resist pattern 5p used as a mask, impurity implantation is performed to form theimpurity region 34 a and impurity region 34 b of the I/O transistor 30and the impurity region 54 a and impurity region 54 b of the logictransistor 50. This impurity implantation is performed, for example, byimplanting phosphorus under the conditions: the accelerating energy of 8keV and the dose amount of 1×10¹⁶ cm⁻².

Next, the resist pattern 5 p is removed, and as illustrated in FIG. 35,a resist pattern 5 q that covers the element region 30 b of the I/Otransistor 30 and the element region 50 b of the logic transistor 50 isformed. With the resist pattern 5 q used as a mask, impurityimplantation is performed to form the impurity region 44 a and impurityregion 44 b of the memory transistor 40. This impurity implantation isperformed, for example, by implanting arsenic under the conditions: theaccelerating energy of 5 keV and the dose amount of 5×10¹⁵ cm⁻². Use ofsuch conditions makes it possible to obtain the impurity region 44 a andimpurity region 44 b each having a concentration distribution steeperthan that of the impurity region 34 a and impurity region 34 b of theI/O transistor 30 and than that of the impurity region 54 a and impurityregion 54 b of the logic transistor 50. The resist pattern 5 q isremoved after the impurity implantation.

Performing such steps makes it possible to realize a semiconductordevice (nonvolatile memory) provided with the memory transistor 40 whichincludes the impurity region 44 a and impurity region 44 b having asteeper concentration distribution and which is capable of increasingthe generation of hot carriers.

Note that, although one memory transistor 40 is illustrated here, theabove-described semiconductor device may include a plurality of memorytransistors 40, or at least one memory transistor 40 and another memorytransistor. Moreover, although one logic transistor 50 is illustratedhere, the above-described semiconductor device may include a pluralityof logic transistors 50, or at least one logic transistor 50 and anotherlogic transistor. Moreover, although one I/O transistor 30 isillustrated here, the above-described semiconductor device may include aplurality of I/O transistors 30, or at least one I/O transistor 30 andanother I/O transistor.

Here, a case has been taken and described as an example, where theconcentration distribution of the impurity region 44 a and impurityregion 44 b of the memory transistor 40 of the semiconductor device 1Fb(FIG. 33) taken as the second configuration example in the sixthembodiment is made steeper. The approach for making steeper theconcentration distribution of an impurity region in this manner issimilarly applicable also to the memory transistor 10 described in thethird embodiment, and to the memory transistor 40 described in thefourth and fifth embodiments and described in the first configurationexample of the sixth embodiment to obtain the same effect as theabove-described effect.

Next, an eighth embodiment will be described.

Below the channel region of the memory transistor described above, orbelow the impurity region having a relatively-high concentrationprovided below the channel region, a region containing a relativelyhigh-concentration impurity (high-concentration embedded layer) may befurther provided. Here, as the eighth embodiment, a semiconductor deviceincluding a memory transistor provided with such a high-concentrationembedded layer will be described.

FIGS. 36 to 39 illustrate an example of the method for manufacturing thesemiconductor device according to the eighth embodiment. Here, FIG. 36is an exemplary cross sectional schematic view of a main portion of thefirst manufacturing step, FIG. 37 is an exemplary cross sectionalschematic view of the main portion of the second manufacturing step,FIG. 38 is an exemplary cross sectional schematic view of the mainportion of the third manufacturing step, and FIG. 39 is an exemplarycross sectional schematic view of the main portion of the fourthmanufacturing step. Hereinafter, an example of the manufacturing stepsof the semiconductor device according to the eighth embodiment will besequentially described with reference to FIGS. 36 to 39.

Here, a case is taken as an example, where the high-concentrationembedded layer is provided below the impurity region 47 of the memorytransistor 40 of the semiconductor device 1Fb (FIG. 33) taken as thesecond configuration example in the sixth embodiment.

In this case, first, the step as illustrated in FIG. 26 is performed toform, in the semiconductor substrate 2, the well region 6 a, theimpurity region 47 having a relatively-high concentration of the memorytransistor 40, and the impurity region 57 having a relatively-highconcentration of the logic transistor 50. The well region 6 a, theimpurity region 47, and the impurity region 57 each are of a p-type, forexample.

Subsequently, as illustrated in FIG. 36, a resist pattern 5 r, in whichthe element region 40 b of the memory transistor 40 is opened, is formedon the semiconductor substrate 2. With the resist pattern 5 r used as amask, a predetermined impurity implantation is performed on thesemiconductor substrate 2 of the element region 40 b. In this impurityimplantation, an impurity of the same conductivity type as the impurityregion 47 and well region 6 a, i.e., for example, a p-type impurity isimplanted if the impurity region 47 and the well region 6 a are of ap-type. For the impurity implantation, for example, boron is implantedunder the conditions: the accelerating energy of 20 keV and the doseamount of 2.5×10¹³ cm⁻², and is implanted under the conditions: theaccelerating energy of 200 keV and the dose amount of 1×10¹⁴ cm⁻². Withthis impurity implantation, the high-concentration embedded layer 48 isformed below the impurity region 47.

After formation of the high-concentration embedded layer 48 in thismanner, a semiconductor material is epitaxially grown on thesemiconductor substrate 2 to form a semiconductor layer 8 b (non-dopedlayer) on the impurity region 47 of the element region 40 b and on theimpurity region 57 of the element region 50 b, as illustrated in FIG.37. The channel region 46 of the memory transistor 40 and the channelregion 56 of the logic transistor 50 are formed in the semiconductorlayer 8 b. Note that, although a semiconductor layer similar to thesemiconductor layer 8 b of the element region 40 b and element region 50b is formed also in the element region 30 b due to the epitaxial growth,the former semiconductor layer is described as the layer integrated intothe semiconductor substrate 2 for convenience here. After formation ofthe semiconductor layer 8 b, the element isolating region 3 is formedwhich defines the element region 40 b, the element region 30 b, and theelement region 50 b, as illustrated in FIG. 37.

Next, as illustrated in FIG. 38, with a resist pattern 5 u, in which theelement region 30 b is opened, used as a mask, impurity implantation isperformed to form the well region 6 b in the semiconductor substrate 2of the element region 30 b. The well region 6 b is of a p-type, forexample. Subsequently, impurity implantation for adjusting the thresholdvoltage of the I/O transistor 30 may be performed on the semiconductorsubstrate 2 of the element region 30 b.

Thereafter, as described in the second configuration example accordingto the above sixth embodiment, each element is formed in accordance withthe example of steps of FIGS. 8 to 13 described in the third embodimentto obtain a semiconductor device 1G (nonvolatile memory) as illustratedin FIG. 39. Thereafter, the formation of an interlayer insulating film,the formation of a plug, and the formation of an upper wiring layerincluding the conductors, such as a wiring and a via, and the like areperformed.

Note that, although one memory transistor 40 is illustrated here, thesemiconductor device 1G may include a plurality of memory transistors40, or at least one memory transistor 40 and another memory transistor.Moreover, although one logic transistor 50 is illustrated here, thesemiconductor device 1G may include a plurality of logic transistors 50,or at least one logic transistor 50 and another logic transistor.Moreover, although one I/O transistor 30 is illustrated here, thesemiconductor device 1G may include a plurality of I/O transistors 30,or at least one I/O transistor 30 and another I/O transistor.

In the semiconductor device 1G according to the eighth embodiment, thehigh-concentration embedded layer 48 is provided further below theimpurity region 47 having a relatively-high concentration provided belowthe channel region 46 of the memory transistor 40. In the semiconductordevice 1G, the provision of the high-concentration embedded layer 48makes it possible to achieve a reduction of the resistance (wellresistance) in applying a bias (substrate bias) to the semiconductorsubstrate 2. A reduction of the well resistance makes it possible toachieve a reduction of the substrate bias to apply, for example.

Moreover, a reduction of the well resistance makes it possible toachieve a reduction of the area of the memory region of thesemiconductor device 1G and a reduction of the size of the semiconductordevice 1G. This is due to the following reason.

That is, in the memory region of the semiconductor device 1G, a well tapregion electrically connected to the well region in the semiconductorsubstrate 2 is provided on the semiconductor substrate 2, and asubstrate bias is applied from the well tap region on the semiconductorsubstrate 2 to the well region in the semiconductor substrate 2. Thememory region usually includes memory transistors 40 in the numbercorresponding to the memory capacity. The well region is shared by acertain number of memory transistors 40, and from one well tap region,the substrate bias is applied to the well region shared by the certainnumber of memory transistors 40. Accordingly, well tap regions arearranged on the semiconductor substrate 2, in the number correspondingto a total number of memory transistors 40 included in the memoryregion.

If the well resistance is reduced by providing the well region 6 a andhigh-concentration embedded layer 48 in the semiconductor substrate 2 asdescribed above, a certain substrate bias may be applied from one welltap region to a wider range of well region 6 a and high-concentrationembedded layer 48. If the range, in which a certain substrate bias maybe applied from one well tap region, expands, the number of memorytransistors 40, to which a certain substrate bias may be applied fromone well tap region, may be increased. If the number of memorytransistors 40, to which a certain substrate bias may be applied fromone well tap region, may be increased, a total number of well tapregions arranged on the semiconductor substrate 2 may be reduced. If atotal number of well tap regions may be reduced, the area, which thewell tap region on the semiconductor substrate 2 occupies, may bereduced and accordingly the area of a memory region may be reduced.Furthermore, reducing the area of a memory region makes it possible toachieve a reduction of the size of the semiconductor device 1G providedwith the memory region.

Here, a case has been described, where the high-concentration embeddedlayer 48 is provided below the impurity region 47 of the memorytransistor 40 of the semiconductor device 1Fb (FIG. 33) taken as thesecond configuration example in the above sixth embodiment. The approachfor providing the high-concentration embedded layer 48 may be similarlyapplied also to the memory transistor 40 described in the fourth andfifth embodiments, in the first configuration example of the sixthembodiment, and in the seventh embodiment, and the same effect as theabove-described effect is obtained. Moreover, the approach for providingthe high-concentration embedded layer may be applied also to theabove-described memory transistor 10, logic transistor 20, logictransistor 50, and I/O transistor 30, and accordingly may achievereduction of the size of the semiconductor device.

When a transistor not provided with the impurity regions 47 (screen(SCR) layer) as described above is used as the memory transistor of anonvolatile memory, the layout of the memory cell array may berestricted.

Here, FIG. 40 illustrates a memory transistor of a comparative example.FIG. 40 schematically illustrates an exemplary cross section of a mainportion of the memory transistor.

A memory transistor 40B illustrated in FIG. 40 includes a gateinsulating film 41 provided above the semiconductor substrate 2, a gateelectrode 42 provided above the gate insulating film 41, and a sidewallinsulating film 43 provided on the side wall of the gate electrode 42and above the semiconductor substrate 2. The sidewall insulating film 43has a stacked structure of an oxide film 43 a of silicon oxide or thelike and a nitride film 43 b of silicon nitride or the like. The memorytransistor 40B further includes impurity regions 44 a and 44 b which areprovided in the semiconductor substrate 2 on both sides of the gateelectrode 42, respectively, and which function as a source region ordrain region (SD region). The memory transistor 40B also includes LDDregions 45 a and 45 b inside the impurity regions 44 a and 44 b whichfunction as the SD region in the semiconductor substrate 2 below thesidewall insulating film 43. The region between the LDD regions 45 a and45 b serves as a channel region 46B in which a carrier moves.

For example, in the case of the n-channel memory transistor 40B,information is written by injecting and accumulating the hot electrons(hot carriers 49), which are generated in the vicinity of the impurityregion 44 b (drain region), into the sidewall insulating film 43. Inaddition, information is erased by neutralizing the electrons, which areinjected and accumulated in the sidewall insulating film 43, with thehot holes (hot carriers 49) generated in the vicinity of the impurityregion 44 b.

In the memory transistor 40B, in order to efficiently generate the hotcarriers 49 in the vicinity of the impurity region 44 b, a p-typeimpurity is implanted into the surface of the semiconductor substrate 2in which the channel region 46B is formed. Into the semiconductorsubstrate 2 below the sidewall insulating film 43, an n-type impuritytogether with the p-type impurity is implanted, so that the p-typeimpurity is cancelled out by a part of the n-type impurity and then-type impurity regions 45 a and 45 b are formed. In order to stablyform the n-type impurity regions 45 a and 45 b in the semiconductorsubstrate 2 below the sidewall insulating film 43, the concentration ofthe n-type impurity needs to be set high enough against theconcentration of the p-type impurity. Therefore, the concentration ofthe n-type impurity is not allowed to be too low. As the result, only acharacteristic difference of an on-current ratio differing by on theorder of one digit is obtained, between the memory transistor 40B havinginformation written therein and the memory transistor 40B having noinformation written therein. The on-current ratio converted into athreshold voltage is very small, i.e., on the order of 0.1 V.

Moreover, an evaluated variation value AVT of the threshold voltage ofthe memory transistor 40B is on the order of 10 mVpm or more. Note that,the evaluated variation value AVT of the threshold voltage is thegradient (mVpm) of a Pelgrom plot (which is the standard deviation σ(mV)of the threshold voltage plotted against the inverse number (μm⁻¹) ofthe square root of the gate area (channel length L×channel width W)).Assume W/L of the memory transistor 40B is 0.1 μm/0.1 μm, then thevariation in threshold voltage is 0.1 V as one σ and is thus 5σ=0.5 V ina 1M bit memory cell array, which significantly exceeds a shift of thethreshold voltage before and after programming. Therefore, in attemptingto realize a nonvolatile memory using the memory transistor 40B asillustrated in FIG. 40, it is difficult to adopt a NOR type layout forthe memory cell array.

As a layout that makes it possible to stably read information even in amemory cell array using the memory transistor 40B, a twin-bit cell typelayout as illustrated in FIG. 41 may be contemplated.

FIG. 41 illustrates an example of the twin-bit cell type nonvolatilememory. FIG. 41 schematically illustrates an exemplary planar layout ofa main portion of the twin-bit cell type nonvolatile memory.

A nonvolatile memory 60 (semiconductor device) illustrated in FIG. 41includes, as the element region (element region of the semiconductorsubstrate 2 of FIG. 40), a plurality of (e.g., four) active regions 61a, 61 b, 61 c, and 61 d which extends in a direction S and is arrangedin parallel in a direction T perpendicular to the direction S. Wordlines WL1 and WL2 (corresponding to the gate electrode 42 of FIG. 40)extend, via a non-illustrated gate insulating film (corresponding to thegate insulating film 41 of FIG. 40), in the direction T so as totraverse these active regions 61 a, 61 b, 61 c, and 61 d. A sidewallinsulating film 63 (corresponding to the sidewall insulating film 43 ofFIG. 40) is formed on the sidewall of the word lines WL1 and WL2.Impurity regions 64 (corresponding to the impurity regions 44 a and 44 bof FIG. 40) which function as the SD region are formed respectively onboth sides of the word lines WL1 and WL2 of each of the active regions61 a, 61 b, 61 c, and 61 d. Non-illustrated LDD regions (correspondingto the impurity regions 45 a and 45 b of FIG. 40) are formed under thesidewall insulating film 63 and on the inner side of the impurity region64, and a non-illustrated channel region is formed between the LDDregions. The nonvolatile memory 60 includes a plurality of (e.g., eight)memory transistors 70 a, 70 b, 70 c, 70 d, 70 e, 70 f, 70 g, and 70 h(corresponding to the memory transistor 40B of FIG. 40) that is formedfrom these elements.

A plug 71 (contact) extending toward the upper layer is formed on eachimpurity region 64. Each impurity region 64 is connected, via the plug71, to wirings 72 a, 72 b, and 72 c included in the first conductivelayer.

The wiring 72 a has a planar crisscross shape that includes a region 72aa extending in the direction S and a region 72 ab extending in thedirection T. The region 72 aa extends in the direction S between theadjacent active regions 61 a and 61 b. The region 72 ab extends in thedirection T so as to connect the impurity region 64 shared by the memorytransistors 70 a and 70 b of the active region 61 a and the impurityregion 64 shared by the memory transistors 70 c and 70 d of the activeregion 61 b.

The wiring 72 b has a planar crisscross shape that includes a region 72ba extending in the direction S and a region 72 bb extending in thedirection T. The region 72 ba extends in the direction S between theadjacent active regions 61 c and 61 d. The region 72 bb extends in thedirection T so as to connect the impurity region 64 shared by the memorytransistors 70 e and 70 f of the active region 61 c and the impurityregion 64 shared by the memory transistors 70 g and 70 h of the activeregion 61 d. The wiring 72 c is connected, via the plug 71, to theimpurity region 64 on the opposite side of the impurity region 64connected to the wirings 72 a and 72 b of each of the memory transistors70 a, 70 b, 70 c, 70 d, 70 e, 70 f, 70 g, and 70 h.

A via 73 extending toward the upper layer is formed on each of thewirings 72 a, 72 b, and 72 c. The wiring 72 a is connected, via the via73, to a source line SL1 extending in the direction S. The wiring 72 bis connected, via the via 73, to a source line SL2 extending in thedirection S. The wiring 72 c connected to the impurity region 64 of thetransistors 70 a and 70 b of the active region 61 a is connected, viathe via 73, to a bit line BL1 extending in the direction S. The wiring72 c connected to the impurity region 64 of the transistors 70 c and 70d of the active region 61 b is connected, via the via 73, to a bit line/BL1 extending in the direction S. The wiring 72 c connected to theimpurity region 64 of the transistors 70 e and 70 f of the active region61 c is connected, via the via 73, to a bit line BL2 extending in thedirection S. The wiring 72 c connected to the impurity region 64 of thetransistors 70 g and 70 h of the active region 61 d is connected, viathe via 73, to a bit line /BL2 extending in the direction S. The sourcelines SL1 and SL2 and the bit lines BL1, /BL1, BL2, and /BL2 areincluded in the second conductive layer of the nonvolatile memory 60.

In the twin-bit cell type nonvolatile memory 60, a pair of memorytransistors 70 a and 70 c, for example, surrounded by a frame 74 of FIG.41 function as one memory cell. In the memory cell inside the frame 74,pieces of information opposite to each other are written into the memorytransistors 70 a and 70 c connected to the bit lines BL1 and /BL1, andsubsequently the information of one memory cell is read bydifferentially driving the memory transistors 70 a and 70 c. Similarly,in the nonvolatile memory 60, a pair of memory transistors 70 b and 70d, a pair of memory transistors 70 e and 70 g, and a pair of memorytransistors 70 f and 70 h each function as one memory cell.

An example of each of the programming (writing), reading, and erasingoperations of information in the nonvolatile memory 60 will bespecifically described with reference to FIG. 42, FIG. 43, and FIG. 44.Note that, here, the nonvolatile memory 60 provided with the re-channelmemory transistors 70 a, 70 b, 70 c, 70 d, 70 e, 70 f, 70 g, and 70 h istaken as an example.

FIG. 42 is an explanatory view of the programming operation of thetwin-bit cell type nonvolatile memory.

For example, during the programming operation with respect to the memorycell (inside the frame 74) including the pair of memory transistors 70 aand 70 c, the potential of the word line WL1 is set to a high level, thepotential of the bit line BL1 is set to a low level, the potential ofthe bit line /BL1 is set to a high level, and the potential of thesource line SL1 is set to a high level. The potential of the word lineWL2 is set to a low level, the potential of each of the bit lines BL2and /BL2 is set to a low level, and the potential of the source line SL2is set to a low level. Accordingly, hot electrons (hot carriers 49,electric charges 49 a) are injected and accumulated into the sidewallinsulating film 63 of the memory transistor 70 a, thereby performing theprogramming of information.

FIG. 43 is an explanatory view of the reading operation of the twin-bitcell type nonvolatile memory.

During the reading operation with respect to the memory cell (inside theframe 74) including the memory transistors 70 a and 70 c, the potentialof the word line WL1 is set to a high level, the potential of each ofthe bit lines BL1 and /BL1 is set to a high level, and the potential ofthe source line SL1 is set to a low level. The potential of the wordline WL2 is set to a low level, the potential of each of the bit linesBL2 and /BL2 is set to a low level, and the potential of the source lineSL2 is set to a low level. For example, in the memory cell including thememory transistor 70 a where the programming has been performed as inthe above FIG. 42, when such potentials are set, the currents flowingthrough the bit lines BL1 and /BL1 that are connected to the memorytransistors 70 a and 70 c, respectively, will differ from each other inmagnitude. By detecting a difference in magnitude between the currents,the reading of the information of the memory transistor 70 a isperformed.

FIG. 44 is an explanatory view of the erasing operation of the twin-bitcell type nonvolatile memory.

During the erasing operation with respect to the memory cell (inside theframe 74) including the memory transistors 70 a and 70 c, first theprogramming operation as described above is performed on the memorytransistors 70 a and 70 c (not illustrated). After both the memorytransistors 70 a and 70 c of the memory cell are set to a programmedstate, the potential of the word line WL1 is set to be negative, thepotential of each of the bit lines BL1 and /BL1 is set to a low level,and the potential of the source line SL1 is set to a high level. Thepotential of the word line WL2 is set to a low level, the potential ofeach of the bit lines BL2 and /BL2 is set to a low level, and thepotential of the source line SL2 is set to a low level. Thus, theerasing of the information, which has been programmed into both thememory transistors 70 a and 70 c of the memory cell, is performed.

Such a twin-bit cell type nonvolatile memory 60 is designed so as tohave the area as illustrated in the next FIG. 45, for example.

FIG. 45 is an explanatory view of the area of the twin-bit cell typenonvolatile memory.

We now focus on one memory cell including the memory transistors 70 aand 70 c, for example.

In the direction S of this memory cell, assume that the size (gatelength Lg) of the word line WL1 is 0.06 μm, a half-size of each of thewirings 72 a (region 72 ab) and 72 c connected to the plug 71 is 0.04μm, and the size between the word line WL1 and each of the wirings 72 a(region 72 ab) and 72 c is 0.07 μm. In this case, a size U in thedirection S of the memory cell including the memory transistors 70 a and70 c results in 0.28 μm (=0.06 μm+0.04 μm×2+0.07 μm×2).

In the direction T of the memory cell, both the width and pitch of eachof the wirings 72 a (region 72 aa) and 72 c are assumed to be 0.18 μm intotal. In this case, a size V in the direction T of the memory cellincluding the memory transistors 70 a and 70 c results in 0.54 μm (=0.18μm×3).

Accordingly, the area of one memory cell including the memorytransistors 70 a and 70 c of the nonvolatile memory 60 results in 0.1512μm² (=0.28 μm×0.54 μm). The same goes for the other memory cells. Forexample, in the case of the 1M bit nonvolatile memory 60, a total areaof the memory region results in 1.21 mm², the area of a whole memorymacro (including a logic region, an I/O region, and the like in additionto the memory region) results in 3 mm², and thus the occupation ratio ofthe memory region is 40%.

A memory transistor without the SCR layer and a twin-bit cell typenonvolatile memory using this memory transistor have been described, butin contrast, if a memory transistor with the SCR layer is used, thefollowing advantages are obtained.

FIG. 46 illustrates an example of a memory transistor according to anembodiment. FIG. 46 schematically illustrates an exemplary cross sectionof a main portion of the memory transistor.

A memory transistor 40C illustrated in FIG. 46 includes the gateinsulating film 41 provided above the semiconductor substrate 2, thegate electrode 42 provided above the gate insulating film 41, and thesidewall insulating film 43 provided on the side wall of the gateelectrode 42 and above the semiconductor substrate 2. The sidewallinsulating film 43 has a stacked structure of the oxide film 43 a ofsilicon oxide or the like and the nitride film 43 b of silicon nitrideor the like. The memory transistor 40C further includes the impurityregions 44 a and 44 b which are provided in the semiconductor substrate2 on both sides of the gate electrode 42, respectively, and whichfunction as the SD region. The memory transistor 40C also includes theLDD regions 45 a and 45 b inside the impurity regions 44 a and 44 bwhich function as the SD region in the semiconductor substrate 2 belowthe sidewall insulating film 43. The region between the LDD regions 45 aand 45 b serves as the channel region 46 in which a carrier moves. Thememory transistor 40C includes the impurity region 47, as the SCR layer,below the channel region 46.

The channel region 46 of the memory transistor 40C is a non-doped regionwhere any impurity is intentionally not added, or a region where a verylow concentration of impurity is contained. The impurity region 47 belowthe channel region 46 is a region, e.g., a high-concentration p-typeregion, which has the conductivity type different from the LDD regions45 a and 45 b and contains a higher concentration of impurity than thechannel region 46. The dose amount during the impurity implantation ofthe LDD regions 45 a and 45 b is set to a value lower than the doseamount during the impurity implantation of the impurity region 47 whichis the SCR layer.

In the memory transistor 40C, the non-doped or very low concentrationchannel region 46 achieves a lower threshold voltage and also reducesthe variation in the threshold voltage. The evaluated variation valueAVT of the threshold voltage of the memory transistor 40C is on theorder of 4 mVμm, and across the whole 1M bit memory region, thevariation in the threshold voltage is on the order of 5σ=0.2 V, which isvery small as compared with the case where the above-described memorytransistor 40B (FIG. 40) is used.

In the memory transistor 40C, the relatively high-concentration impurityregion 47 efficiently generates the hot carriers 49. The LDD regions 45a and 45 b below the sidewall insulating film 43 are formed in thesemiconductor layer in which the non-doped or very low concentrationchannel region 46 is formed (FIGS. 63 and 64). The semiconductor layer,in which the non-doped or very low concentration channel region 46 isformed, suppresses the diffusion of the impurity, e.g., p-type impurity,from the impurity region 47. Therefore, even if the impurityimplantation of the LDD regions 45 a and 45 b, e.g., implantation of ann-type impurity, is performed under the condition of a lower doseamount, the conductivity type of the LDD regions 45 a and 45 b alwaysresults in the conductivity type of the impurity, e.g., an n-type, whichthus does not cause any offset. Accordingly, in the memory transistor40C, a higher on-current may be stably achieved in a state where theelectric charge 49 a is not trapped in the sidewall insulating film 43,and a larger variation in the threshold voltage may be caused in a statewhere the electric charge 49 a is trapped in the sidewall insulatingfilm 43.

Here, an example of the concentration profile is illustrated in FIGS.47A to 47D when phosphorus is used for the impurity of the LDD region.

FIGS. 47A to 47D each illustrate the concentration profile obtained byTCAD (Technology Computer Aided Design) when phosphorus for the LDDregion has been implanted into a semiconductor substrate having the SCRlayer formed by impurity implantation (FIG. 61), having thesemiconductor layer formed by epitaxial growth (FIG. 63), and having thegate electrode formed via the gate insulating film (FIG. 64).

The following impurity implantation conditions are used in the formationof the SCR layer. Germanium is implanted under the conditions: theaccelerating energy of 30 keV and the dose amount of 5×10¹⁴ cm⁻². Carbonis implanted under the conditions: the accelerating energy of 5 keV andthe dose amount of 5×10¹⁴ cm⁻². Boron is implanted under the conditions:the accelerating energy of 20 keV and the dose amount of 4×10¹³ cm⁻².

FIG. 47A illustrates the concentration profile when the implantation ofphosphorus under the conditions: the accelerating energy of 35 keV andthe dose amount of 2.5×10¹² cm⁻², is performed from four directions witha tilt angle of 28° to form the LDD region. FIG. 47B illustrates theconcentration profile when the implantation of phosphorus under theconditions: the accelerating energy of 35 keV and the dose amount of1.0×10¹² cm⁻², is performed from four directions with the tilt angle of28° to form the LDD region. FIG. 47C illustrates the concentrationprofile when the implantation of phosphorus under the conditions: theaccelerating energy of 35 keV and the dose amount of 5.0×10¹¹ cm⁻² isperformed from four directions with the tilt angle of 28° to form theLDD region. FIG. 47D illustrates the concentration profile when theimplantation of phosphorus under the conditions: the accelerating energyof 35 keV and the dose amount of 2.5×10¹¹ cm⁻² is performed from fourdirections with the tilt angle of 28° to form the LDD region.

In FIGS. 47A to 47D, the horizontal axis represents the depth(μm) fromthe surface of the semiconductor substrate while the vertical axisrepresents the concentration(cm⁻³) of the p-type and n-type impurities.Note that, in FIGS. 47A to 47D, the concentration profile of the p-typeimpurity is drawn with a thick chain line, the concentration profile ofthe n-type impurity is drawn with a thick solid line, and thecancelled-out concentration profile of the p-type and n-type impuritiesis drawn with a thin dotted line.

For example, as illustrated in FIG. 47A, an n-type impurity (phosphorus)implanted for formation of the LDD region is present closer to the frontside of the semiconductor substrate than the p-type impurity (boron)implanted for formation of the SCR layer. Under the implantingconditions of the n-type impurity as in FIG. 47A, the n-type LDD regionis stably formed in the vicinity of the surface of the semiconductorsubstrate having the p-type SCR layer formed therein. Similarly, alsounder the implanting conditions of the n-type impurity as in FIGS. 47Band 47C, the n-type impurity is present closer to the front side of thesemiconductor substrate than the p-type impurity, and the n-type LDDregion is stably formed in the vicinity of the surface of thesemiconductor substrate having the p-type SCR layer formed therein.Furthermore, also under the implanting conditions of the n-type impurityas in FIG. 47D, the n-type LDD region is formed in the vicinity of thesurface of the semiconductor substrate having the p-type SCR layerformed therein. According to FIGS. 47A to 47D, even in a very lowconcentration, e.g., 1×10¹⁷ cm⁻³ or less, the n-type LDD region may beformed in the vicinity of the surface of the semiconductor substratehaving the p-type SCR layer formed therein.

Moreover, an example of the concentration profile is illustrated inFIGS. 48A to 48D when arsenic is used for the impurity of the LDDregion.

FIGS. 48A to 48D each illustrate the concentration profile obtained byTCAD when arsenic for the LDD region has been implanted into asemiconductor substrate having the SCR layer formed by impurityimplantation (FIG. 61), having the semiconductor layer formed byepitaxial growth (FIG. 63), and having the gate electrode formed via thegate insulating film (FIG. 64).

The following impurity implantation conditions are used in the formationof the SCR layer. Germanium is implanted under the conditions: theaccelerating energy of 30 keV and the dose amount of 5×10¹⁴ cm⁻². Carbonis implanted under the conditions: the accelerating energy of 5 keV andthe dose amount of 5×10¹⁴ cm⁻². Boron is implanted under the conditions:the accelerating energy of 20 keV and the dose amount of 4×10¹³ cm⁻².

FIG. 48A illustrates the concentration profile when the implantation ofarsenic under the conditions: the accelerating energy of 10 keV and thedose amount of 2.5×10¹² cm⁻², is performed four times with the tiltangle of 0° to form the LDD region. FIG. 48B illustrates theconcentration profile when the implantation of arsenic under theconditions: the accelerating energy of 10 keV and the dose amount of1.0×10¹² cm⁻², is performed four times with the tilt angle of 0° to formthe LDD region. FIG. 48C illustrates the concentration profile when theimplantation of arsenic under the conditions: the accelerating energy of10 keV and the dose amount of 5.0×10¹¹ cm⁻², is performed four timeswith the tilt angle of 0° to form the LDD region. FIG. 48D illustratesthe concentration profile when the implantation of arsenic under theconditions: the accelerating energy of 10 keV and the dose amount of2.5×10¹¹ cm⁻², is performed four times with the tilt angle of 0° to formthe LDD region.

In FIGS. 48A to 48D, the horizontal axis represents the depth(μm) fromthe surface of the semiconductor substrate while the vertical axisrepresents the concentration(cm⁻³) of the p-type and n-type impurities.Note that, in FIGS. 48A to 48D, the concentration profile of the p-typeimpurity is drawn with a thick chain line, the concentration profile ofthe n-type impurity is drawn with a thick solid line, and thecancelled-out concentration profile of the p-type and n-type impuritiesis drawn with a thin dotted line.

For example, as illustrated in FIG. 48A, the n-type impurity (arsenic)implanted for formation of the LDD region is present closer to the frontside of the semiconductor substrate than the p-type impurity (boron)implanted for formation of the SCR layer. Under the implantingconditions of the n-type impurity as in FIG. 48A, the n-type LDD regionis stably formed in the vicinity of the surface of the semiconductorsubstrate having the p-type SCR layer formed therein. Similarly, alsounder the implanting conditions of the n-type impurity as in FIGS. 48Bto 48D, the n-type impurity is present closer to the front side of thesemiconductor substrate than the p-type impurity, and the n-type LDDregion is stably formed in the vicinity of the surface of thesemiconductor substrate having the p-type SCR layer formed therein.

FIG. 49 illustrates an example of the programming characteristics of thememory transistor with the SCR layer.

FIG. 49 illustrates a relationship between the gate voltage Vg(V) andthe read current (drain current) Id(A/μm), the relationship beingobtained by the reading operation before and after the programming, ofthe memory transistor 40C with the impurity region 47 which is the SCRlayer illustrated in the above FIG. 46.

The programming operation with respect to the memory transistor 40C isperformed under the voltage conditions where both the impurity region 44a and the semiconductor substrate 2 are set to 0 V and both the gateelectrode 42 and the impurity region 44 b are set to 4 V (programmingvoltage Vp=4 V). After the programming operation is performed with aprogram time Tp=1 μs under the voltage conditions described above, thereading operation is performed by setting the impurity region 44 b andthe semiconductor substrate 2 to 0 V and applying a predeterminedvoltage to the gate electrode 42 and applying 0.5 V (drain voltageVd=0.5 V) to the impurity region 44 a. The relationship between the gatevoltage Vg and the read current Id during the reading operation isillustrated in FIG. 49.

The threshold voltage before programming (the initial threshold voltage)of the memory transistor 40C is on the order of 0.5 V. FIG. 49 revealsthat in the memory transistor 40C, a sufficient on-current of 0.5 μA ormore is obtained even with the gate voltage Vg=1.0 V. If the programmingoperation with a relatively low voltage and short time, such as thevoltage Vp=4 V and program time Tp=1 μs as described above, is performedwith respect to the memory transistor 40C, the threshold voltage afterprogramming will shift to a higher Vg side by on the order of 1 V. Theon-current ratio between before and after programming is significantlylarge by around four digits as compared with the above-described memorytransistor 40B without the SCR layer (impurity region 47). This shift ofthe threshold voltage in the memory transistor 40C before and afterprogramming is significantly larger than the variation in thresholdvoltage across the whole memory region in the case of the memory regionof a 1M-bit memory, for example. Accordingly, the memory transistor 40Cdoes not need to adopt the twin-bit cell type configuration.

The memory transistor 40C will be further described.

FIG. 50 illustrates an example of the erasing characteristics of thememory transistor with the SCR layer.

FIG. 50 illustrates a relationship between the gate voltage Vg(V) andthe read current Id(A/μm), the relationship being obtained in thereading operation before and after the programming operation and afterthe erasing operation, of the memory transistor 40C illustrated in theabove FIG. 46 with the impurity region 47 which is the SCR layer.

The programming operation with respect to the memory transistor 40C isperformed with the program time Tp set to 1 μs under the voltageconditions where both the impurity region 44 a and the semiconductorsubstrate 2 are set to 0 V and both the gate electrode 42 and theimpurity region 44 b are set to 4 V (programming voltage Vp=4 V). Theerasing operation after the programming operation is performed with theerasing time Te set to 1 ms, 10 ms, 100 ms, and 1 s, respectively, underthe voltage conditions where both the impurity region 44 a and thesemiconductor substrate 2 are set to 0 V, the gate electrode 42 is setto −5 V and the impurity region 44 b is set to 5 V (erasing voltage Ve=5V). The reading operation before and after programming and after erasingis performed by setting the impurity region 44 b and the semiconductorsubstrate 2 to 0 V and applying a predetermined voltage to the gateelectrode 42 and applying 0.5 V (drain voltage Vd=0.5 V) to the impurityregion 44 a. The relationship between the gate voltage Vg and the readcurrent Id during the reading operation is illustrated in FIG. 50.

As described in the above FIG. 49, if the programming operation isperformed under the conditions: the programming voltage Vp=4 V and theprogram time Tp=1 μs, the threshold voltage after programming will shiftto a higher Vg side, by on the order of 1 V, than before programming(than the initial value).

If with respect to the memory transistor 40C after programming, theerasing operation is performed under the conditions: the erasing voltageVe=5 V and the erasing time of 1 ms, the threshold voltage after theerasing operation shifts back, by on the order of 0.4 V, to a lower Vgside, as illustrated in FIG. 50. If with respect to the memorytransistor 40C after programming, the erasing operation is performedwith a longer erasing time of 10 ms, the threshold voltage after erasingwill return to the value before the programming (to the initial value).In the memory transistor 40C, even if the erasing operation is performedwith a further longer erasing time of 100 ms or 1 s, after programming,the threshold voltage after erasing hardly shifts as illustrated in FIG.50 and thus the memory transistor 40C will not be in an over-erasedstate. As described above, in the transistor 40C with the SCR layer(impurity region 47), an excellent erasing operation may be performedunder the conditions: the erasing voltage Ve=5 V, the erasing time of 10ms or more.

FIGS. 51A and 51B to FIGS. 53A and 53B each illustrate the LDD regionconcentration dependence of the programming characteristics of thememory transistor with the SCR layer.

FIG. 51A illustrates the programming characteristics of the memorytransistor 40C in the case where boron has been implanted into theimpurity region 47 which is the SCR layer, phosphorus has been implantedinto the LDD regions 45 a and 45 b, and then arsenic has been implantedinto the impurity regions 44 a and 44 b which are the SD regions. Here,the boron of the SCR layer is implanted under the conditions: theaccelerating energy of 20 keV and the dose amount of 2.5×10¹³ cm⁻². Thephosphorus of the LDD regions 45 a and 45 b is implanted from fourdirections under the conditions: the accelerating energy of 35 keV, thedose amount of 2.5×10¹² cm⁻², and the tilt angle of 28°.

The programming operation is performed with the program time Tp set to10 μs under the voltage conditions where both the impurity region 44 aand the semiconductor substrate 2 are set to 0 V and both the gateelectrode 42 and the impurity region 44 b are set to 4 V (programmingvoltage Vp=4 V). The reading operation is performed by setting theimpurity region 44 b and the semiconductor substrate 2 to 0 V andapplying a predetermined gate voltage Vg to the gate electrode 42 andapplying the drain voltage Vd=0.5 V to the impurity region 44 a. FIG.51A illustrates a relationship between the gate voltage Vg(V) and theread current Id(A/μm), the relationship being obtained in the readingoperation before and after programming. FIG. 51B illustrates theconcentration profiles, obtained by TCAD, of the p-type and n-typeimpurities of the impurity region 47 and LDD regions 45 a and 45 b inthe memory transistor 40C having the Id-Vg characteristics of FIG. 51A.

FIG. 52A illustrates the programming characteristics of the memorytransistor 40C in the case where boron has been implanted into theimpurity region 47 which is the SCR layer, arsenic has been implantedinto the LDD regions 45 a and 45 b, and then arsenic has been implantedinto the impurity regions 44 a and 44 b which are the SD regions. Here,the boron of the SCR layer is implanted under the conditions: theaccelerating energy of 20 keV and the dose amount of 2.5×10¹³ cm⁻². Thearsenic of the LDD regions 45 a and 45 b is implanted four times underthe conditions: the accelerating energy of 10 keV, the dose amount of5×10¹¹ cm⁻², and the tilt angle of 0°.

The programming operation is performed with the program time Tp set to10 μs under the voltage conditions where both the impurity region 44 aand the semiconductor substrate 2 are set to 0 V and both the gateelectrode 42 and the impurity region 44 b are set to 4 V (programmingvoltage Vp=4 V). The reading operation is performed by setting theimpurity region 44 b and the semiconductor substrate 2 to 0 V andapplying a predetermined gate voltage Vg to the gate electrode 42 andapplying the drain voltage Vd=0.5 V to the impurity region 44 a. FIG.52A illustrates a relationship between the gate voltage Vg(V) and theread current Id(A/μm), the relationship being obtained in the readingoperation before and after programming. FIG. 52B illustrates theconcentration profile, obtained by TCAD, of the p-type and n-typeimpurities of the impurity region 47 and LDD regions 45 a and 45 b inthe memory transistor 40C having the Id-Vg characteristics of FIG. 52A.

FIG. 53A illustrates the programming characteristics of the memorytransistor 40C in the case where boron has been implanted into theimpurity region 47 which is the SCR layer, arsenic has been implantedinto the LDD regions 45 a and 45 b, and arsenic has been implanted intothe impurity regions 44 a and 44 b which are the SD regions. Here, theboron of the SCR layer is implanted under the conditions: theaccelerating energy of 20 keV and the dose amount of 2.5×10¹³ cm⁻². Thearsenic of the LDD regions 45 a and 45 b is implanted four times underthe conditions: the accelerating energy of 10 keV, the dose amount of1×10¹³ cm⁻², and the tilt angle of 0°.

The programming operation is performed with the program time Tp set to10 μs under the voltage conditions where both the impurity region 44 aand the semiconductor substrate 2 are set to 0 V and both the gateelectrode 42 and the impurity region 44 b are set to 4 V (programmingvoltage Vp=4 V). The reading operation is performed by setting theimpurity region 44 b and the semiconductor substrate 2 to 0 V andapplying the predetermined gate voltage Vg to the gate electrode 42 andapplying the drain voltage Vd=0.5 V to the impurity region 44 a. FIG.53A illustrates a relationship between the gate voltage Vg(V) and theread current Id(A/μm), the relationship being obtained in the readingoperation before and after programming. FIG. 53B illustrates theconcentration profiles, obtained by TCAD, of the p-type and n-typeimpurities of the impurity region 47 and LDD regions 45 a and 45 b inthe memory transistor 40C having the Id-Vg characteristics of FIG. 53A.

FIG. 51A reveals that in the memory transistor 40C with the LDD regions45 a and 45 b that are formed by implanting phosphorus under theabove-described conditions, after programming with Vp=4 V and Tp=10 μs,the threshold voltage shifts relatively largely from the value beforethe programming (the initial value). Moreover, FIG. 52A reveals thatalso in the memory transistor 40C with the LDD regions 45 a and 45 bthat are formed by implanting arsenic under the above-describedconditions, after programming with Vp=4 V and Tp=10 μs, the thresholdvoltage shifts relatively largely from the value before the programming(the initial value). In contrast, FIG. 53A reveals that in the casewhere the LDD regions 45 a and 45 b have been formed by implantingarsenic in a higher concentration than the case of FIG. 52A, afterprogramming with Vp=4 V and Tp=10 μs, the threshold voltage hardlyshifts from the value before the programming (the initial value).

In the memory transistor 40C whose threshold voltage shifts relativelylargely as in FIGS. 51A and 52A, there is a relatively low concentrationn-type impurity (LDD region) in the vicinity of the surface of thesemiconductor substrate 2 having the p-type impurity (SCR layer)therein, as in FIGS. 51B and 52B. In contrast, in the memory transistor40C whose threshold voltage hardly shifts as in FIG. 53A, there is arelatively high concentration n-type impurity (LDD region) in thevicinity of the surface of the semiconductor substrate 2 having thep-type impurity (SCR layer) therein, as in FIG. 53B.

FIGS. 51A and 51B to FIGS. 53A and 53B reveal that in the memorytransistor 40C, if the LDD regions 45 a and 45 b are of a relatively lowconcentration, a relatively high programming speed is obtained, while ifthe LDD regions 45 a and 45 b are of an excessively high concentration,the programming speed will decrease. From the viewpoint of suppressing asignificant decrease in programming speed, the concentration of the LDDregions 45 a and 45 b is set to 5×10¹⁸ cm⁻³ or less, preferably 5×10¹⁷cm⁻³ or less, more preferably 3×10¹⁷ cm⁻³ or less, and further 1×10¹⁷cm⁻³ or less.

FIGS. 54 and 55 each illustrate the SCR layer concentration dependenceand SD region impurity type dependence of the programmingcharacteristics of the memory transistor with the SCR layer.

In FIG. 54, the Id-Vg characteristic before programming (the initialId-Vg characteristic) illustrated in the above FIG. 51A is drawn with asolid line X1 i, while the Id-Vg characteristic after programming isdrawn with a chain line X1 p. Additionally, in FIG. 54, the Id-Vgcharacteristic before programming (the initial Id-Vg characteristic) ofthe memory transistor 40C with the impurity region 47 of the SCR layerhaving a higher concentration than in the case of the above FIG. 51A isdrawn with a thick solid line X2 i, while the Id-Vg characteristic afterprogramming is drawn with a thick chain line X2 p. Boron is implantedinto the high concentration SCR layer under the conditions: theaccelerating energy of 20 keV and the dose amount of 4.0×10¹³ mm⁻². Inthe memory transistor 40C exhibiting the Id-Vg characteristics of FIG.54, arsenic is implanted into the impurity regions 44 a and 44 b of theSD region. Note that, the programming operation and reading operationare performed under the same conditions as in the case of the above FIG.51A.

FIG. 55 illustrates the Id-Vg characteristics of the memory transistor40C when the impurity implantation conditions (impurity concentration)of the impurity region 47 of the SCR layer and the LDD regions 45 a and45 b are the same as in the case of FIG. 54 and not arsenic butphosphorus has been implanted into the impurity regions 44 a and 44 b ofthe SD region.

That is, the first memory transistor 40C includes the SCR layer of arelatively low concentration, and boron is implanted into the SCR layerunder the conditions: the accelerating energy of 20 keV and the doseamount of 2.5×10¹³ cm⁻². Phosphorus is implanted into the LDD regions 45a and 45 b of the first memory transistor 40C four times under theconditions: the accelerating energy of 35 keV, the dose amount of2.5×10¹² cm⁻², and the tilt angle of 28°, and phosphorus is implantedinto the SD region. In FIG. 55, the Id-Vg characteristic beforeprogramming (the initial Id-Vg characteristic) of the first memorytransistor 40C is drawn with a solid line Y1 i, while the Id-Vgcharacteristic after programming is drawn with a chain line Y1 p. Notethat, the programming operation and reading operation are performedunder the same conditions as in the case of the above FIG. 54.

Moreover, the second memory transistor 40C includes the SCR layer of arelatively high concentration, and boron is implanted into the SCR layerunder the conditions: the accelerating energy of 20 keV and the doseamount of 4.0×10¹³ cm⁻². Phosphorus is implanted into the LDD regions 45a and 45 b of the second memory transistor 40C four times under theconditions: the accelerating energy of 35 keV, the dose amount of2.5×10¹² cm⁻², and the tilt angle of 28°, and phosphorus is implantedinto the SD region. In FIG. 55, the Id-Vg characteristic beforeprogramming (the initial Id-Vg characteristic) of the second memorytransistor 40C is drawn with a thick solid line Y2 i, while the Id-Vgcharacteristic after programming is drawn with a thick chain line Y2 p.Note that, the programming operation and reading operation are performedunder the same conditions as in the case of the above FIG. 54.

FIGS. 54 and 55 reveal that in either the case where the impurityimplanted into the SD region is arsenic or the case where it isphosphorus, a shift in the threshold voltage before and afterprogramming under the same conditions increases more in the case wherethe dose amount of the SCR layer is increased to increase the impurityconcentration. Moreover, FIGS. 54 and 55 reveal that in the case wherethe impurity implanted into SD region is phosphorus (FIG. 55), thejunction leak may be further reduced to reduce an off-current Ioff thanthe case where the impurity implanted into SD region is arsenic (FIG.54).

FIG. 56 illustrates another example of the programming characteristicsof the memory transistor with the SCR layer.

FIG. 56 illustrates the Id-Vg characteristics that are drawn with thesolid line Y1 i and chain line Y1 p in the above FIG. 55. That is, inFIG. 56, the Id-Vg characteristics before and after programming of thefirst memory transistor 40C described in the above FIG. 55 are drawnwith the solid line Y1 i and chain line Y1 p, respectively.Additionally, in FIG. 56, the Id-Vg characteristic when a substrate bias(back bias) Vbb of −3.0 V has been applied to the semiconductorsubstrate 2 during the programming operation of the first memorytransistor 40C is drawn with a thick chain line Zip. Note that, theprogramming operation and reading operation are performed under the sameconditions as in the case of the above FIG. 55.

FIG. 56 reveals that in the case where the substrate bias Vbb is appliedduring the programming operation (thick chain line Z1 p), the thresholdvoltage after programming shifts to a significantly higher Vg side withrespect to the threshold voltage before programming than the case wherethe substrate bias Vbb is not applied (chain line Y1 p). Applying thesubstrate bias Vbb during the programming operation makes it possible toachieve a significant improvement in the programming speed.

As described above, in the memory transistor 40C having the impurityregion 47 as the SCR layer, the impurity implanted into the LDD regions45 a and 45 b, e.g., n-type impurity such as phosphorus or arsenic, maybe set in a very low concentration. Furthermore, adjustment of the typeand concentration of an impurity implanted into each of the LDD regions45 a and 45 b, impurity region 47 (SCR layer), and impurity regions 44 aand 44 b (SD regions) or further application of the substrate bias Vbbmakes it possible to achieve an improvement in the characteristics ofthe memory transistor 40C. For example, an increase of the variation inthe threshold voltage before and after programming of the memorytransistor 40C, i.e., an increase of the programming speed, may beachieved. Moreover, in the memory transistor 40C, the over-erasing maybe suppressed. Therefore, in the nonvolatile memory using the memorytransistor 40C, a relatively complicated processing operation, such aserase verification, does not need to be performed after the erasingoperation.

Subsequently, a nonvolatile memory using the memory transistor 40C withthe SCR layer as described above will be described.

FIG. 57 illustrates an example of the nonvolatile memory using thememory transistor with the SCR layer. FIG. 57 schematically illustratesan exemplary planar layout of a main portion of the nonvolatile memoryusing the memory transistor with the SCR layer.

A nonvolatile memory 80 (semiconductor device) illustrated in FIG. 57includes, as an element region (element region of the semiconductorsubstrate 2 of FIG. 46), a plurality of (e.g., four) active regions 81a, 81 b, 81 c, and 81 d which extends in the direction S and is arrangedin parallel in the direction T perpendicular to the direction S. Theword lines WL1, WL2 (corresponding to the gate electrode 42 of FIG. 46)extend via a non-illustrated gate insulating film (corresponding to thegate insulating film 41 of FIG. 46) in the direction T so as to traversethese active regions 81 a, 81 b, 81 c, and 81 d. A sidewall insulatingfilm 83 (corresponding to the sidewall insulating film 43 of FIG. 46) isformed on the sidewall of the word lines WL1 and WL2. An impurity region84 (corresponding to the impurity regions 44 a and 44 b of FIG. 46)which functions as the SD region is formed respectively on both sides ofthe word lines WL1 and WL2 of each of the active regions 81 a, 81 b, 81c, and 81 d. A non-illustrated LDD region (corresponding to the impurityregions 45 a and 45 b of FIG. 46) is formed under the sidewallinsulating film 83 and on the inner side of the impurity region 84, anda non-illustrated channel region is formed between the LDD regions.Moreover, a non-illustrated impurity region serving as the SCR layer isformed below the channel region. The nonvolatile memory 80 includes aplurality of (e.g., eight) memory transistors 90 a, 90 b, 90 c, 90 d, 90e, 90 f, 90 g, and 90 h (corresponding to the memory transistor 40C ofFIG. 46) that is formed from these elements.

A plug 91 (contact) extending toward the upper layer is formed on eachimpurity region 84. Each impurity region 84 is connected, via the plug91, to the wirings 92 a and 92 b included in the first conductive layer.

The wiring 92 a extends in the direction T. The wiring 92 a isconnected, via the plug 91, to the impurity region 84 shared by thememory transistors 90 a and 90 b of the active region 81 a. The wiring92 a is connected, via the plug 91, to the impurity region 84 shared bythe memory transistors 90 c and 90 d of the active region 81 b. Thewiring 92 a is connected, via the plug 91, to the impurity region 84shared by the memory transistors 90 e and 90 f of the active region 81c. The wiring 92 a is connected, via the plug 91, to the impurity region84 shared by the memory transistors 90 g and 90 h of the active region81 d. The wiring 92 a is used as the source line (SL1).

The wiring 92 b is connected, via the plug 91, to the impurity region 84on the opposite side of the impurity region 84 connected to the sourceline SL1 of each of the memory transistors 90 a, 90 b, 90 c, 90 d, 90 e,90 f, 90 g, and 90 h.

A via 93 extending toward the upper layer is formed on each wiring 92 b.The wiring 92 b connected to the impurity region 84 of the transistors90 a and 90 b of the active region 81 a is connected, via the via 93, tothe bit line BL1 which extends in the direction S. The wiring 92 bconnected to the impurity region 84 of the transistors 90 c and 90 d ofthe active region 81 b is connected, via the via 93, to the bit line BL2which extends in the direction S. The wiring 92 b connected to theimpurity region 84 of the transistors 90 e and 90 f of the active region81 c is connected, via the via 93, to the bit line BL3 which extends inthe direction S. The wiring 92 b connected to the impurity region 84 ofthe transistors 90 g and 90 h of the active region 81 d is connected,via the via 93, to the bit line BL4 which extends in the direction S.The bit lines BL1, BL2, BL3, and BL4 are included in the secondconductive layer of the nonvolatile memory 80.

In the nonvolatile memory 80, the individual memory transistors 90 a, 90b, 90 c, 90 d, 90 e, 90 f, 90 g, and 90 h function as one memory cell.An example of each of the programming, reading, and erasing operationsof information in the nonvolatile memory 80 will be specificallydescribed with reference to FIGS. 58A and 58B, FIGS. 59A and 59B, andFIGS. 60A and 60B. Note that, here, the nonvolatile memory 80 providedwith the n-channel memory transistors 90 a, 90 b, 90 c, 90 d, 90 e, 90f, 90 g, and 90 h is taken as an example.

FIGS. 58A and 58B are explanatory views of the programming operation ofthe nonvolatile memory using the memory transistor with the SCR layer.FIG. 58A schematically illustrates a planar layout of a main portion ofthe nonvolatile memory during the programming operation, while FIG. 58Bschematically illustrates a cross section of the main portion of thenonvolatile memory during the programming operation. Note that, FIG. 58Bis a cross sectional schematic view along a line L1-L1 of FIG. 58A.

For example, during the programming operation with respect to the memorytransistor 90 a (memory cell) with the impurity region 87 serving as theSCR layer, the potential of the word line WL1 on the gate insulatingfilm 81 is set to a high level (4 V to 5 V), the potential of the bitline BL1 is set to a low level (0 V), and the potential of the sourceline SL1 is set to a high level (4 V to 5 V). The potential of theunselected word line WL2 is set to a low level (0 V), and the potentialof the unselected bit lines BL2 to BL4 is set to a high level (4 V to 5V). Thus, the hot electrons (hot carriers 49, electric charges 49 a) areinjected and accumulated into the sidewall insulating film 83 above theLDD region 85 on the source line SL1 side of the memory transistor 90 a,thereby performing the programming of information.

Because the LDD region 85 of the memory transistor 90 a is in a very lowconcentration, the electric field of the LDD region 85 is relativelysmall. On the other hand, because the impurity region 84 which is the SDregion adjacent to the outside of the LDD region 85 is in a highconcentration, the electric field abruptly increases at an edge of theimpurity region 84. As the result, the hot electrons are efficientlygenerated in the vicinity of the impurity region 84 (drain) on thesource line SL1 side, and the generated hot electros are efficientlyinjected into the sidewall insulating film 83 above the LDD region 85 onthe source line SL1 side.

FIGS. 59A and 59B are explanatory views of the reading operation of thenonvolatile memory using the memory transistor with the SCR layer. FIG.59A schematically illustrates a planar layout of a main portion of thenonvolatile memory during the reading operation, while FIG. 59Bschematically illustrates a cross section of the main portion of thenonvolatile memory during the reading operation. Note that, FIG. 59B isthe cross sectional schematic view along a line L2-L2 of FIG. 59A.

During the reading operation with respect to the memory transistor 90 a,the potential of the word line WL1 is set to a high level (0.5 V), thepotential of the bit line BL1 is set to a high level (0.5 V), and thepotential of the source line SL1 is set to a low level (0 V). Thepotential of the unselected word line WL2 is set to a low level (0 V),and the potential of the unselected bit lines BL2 to BL4 is set to a lowlevel (0 V). Note that, FIGS. 59A and 59B illustrate the memorytransistor 90 a in which the electric charges 49 a are injected andaccumulated into the sidewall insulating film 83. The reading ofinformation of the memory transistor 90 a is performed by detecting acurrent which flows from the bit line BL1 side to the source line SL1side when such potentials are set.

FIGS. 60A and 60B are explanatory views of the erasing operation of thenonvolatile memory using the memory transistor with the SCR layer. FIG.60A schematically illustrates a planar layout of a main portion of thenonvolatile memory during the erasing operation, while FIG. 60Bschematically illustrates a cross section of the main portion of thenonvolatile memory during the erasing operation. Note that, FIG. 60B isthe cross sectional schematic view along a line L3-L3 of FIG. 60A.

During the erasing operation with respect to the memory transistor 90 a,first the programming operation as described above is performed on thememory transistors 90 a, 90 c, 90 e, and 90 g connected to the word lineWL1 (not illustrated). After the memory transistors 90 a, 90 c, 90 e,and 90 g are set to a programmed state, the potential of the word lineWL1 is set to negative (−5 V to −6 V), the potential of the bit linesBL1 to BL4 is set to a low level (0 V), and the potential of the sourceline SL1 is set to a high level (5 V to 6 V). The potential of theunselected word line WL2 is set to a low level (0 V). Thus, erasing ofthe information, which has been programmed into the memory transistors90 a, 90 c, 90 e, and 90 g connected to the word line WL1, is performed.

During the erasing operation, the hot holes (hot carriers 49) aregenerated in the vicinity of the impurity region 84 on the source lineSL1 side to neutralize the electrons (electric charges 49 a) accumulatedin the sidewall insulating film 83 above the LDD region 85 on the sourceline SL1 side. Because the hot holes are generated in the vicinity ofthe impurity region 84 on the source line SL1 side, the influence on thethreshold voltage in regions away from the impurity region 84 isreduced. Accordingly, unless a gate length Lg of the word line WL1 isexcessively reduced, the threshold voltage as a whole is positive, i.e.,the off-current of the memory transistor 90 a will not significantlyexceed the initial value.

Note that, in a floating gate type memory transistor, if the erasingtime is extended, an over-erasing problem will occur in which thethreshold voltage becomes negative, but in a memory transistor with theSCR layer as described above, such a problem may be avoided unless thegate length Lg is set excessively small.

In the nonvolatile memory 80 in which each of the programming, reading,and erasing operations may be performed in a manner described above, areduction in the area of the memory region may be achieved as comparedwith the twin-bit cell type nonvolatile memory 60 described above. Here,we will focus on one memory cell, e.g., the memory transistor 90 a, inthe nonvolatile memory 80 illustrated in FIG. 57.

In the direction S of the memory transistor 90 a, assume that the size(gate length Lg) of the word line WL1 is 0.06 μm, a half-size of each ofthe source line SL1 and wiring 92 b connected to the plug 91 is 0.04 μm,and the size between the word line WL1 and each of the source line SL1and wiring 92 b is 0.07 μm. In this case, the size U in the direction Sof the memory transistor 90 a results in 0.28 μm (=0.06 μm+0.04μm×2+0.07 μm×2).

In the direction T of the memory transistor 90 a, if the width and pitchof the wiring 92 b is assumed to be 0.18 μm in total, a size V in thedirection T of the memory transistor 90 a results in 0.18 μm.

Accordingly, the area of one memory cell of the nonvolatile memory 80results in 0.0504 μm² (=0.28 μm×0.18 μm). The same goes for the othermemory cells. For example, in the case of the 1M bit nonvolatile memory80, a total area of the memory region is 0.402 mm², the area of a wholememory macro (including a logic region, an I/O region, and the like inaddition to the memory region) is 1.34 mm², and thus the occupationratio of the memory region is 30%. In the nonvolatile memory 80, thearea of the memory region may be reduced to one third as compared withthe twin-bit cell type nonvolatile memory 60.

An example of the configuration of and method for manufacturing anonvolatile memory using the memory transistor 40C (90 a or the like)will be further described with reference to FIGS. 61 to 65.

FIGS. 61 to 65 illustrate an example of the method for manufacturing thenonvolatile memory. Here, FIG. 61 is an exemplary cross sectionalschematic view of a main portion in the first manufacturing step, FIG.62 is an exemplary cross sectional schematic view of the main portion inthe second manufacturing step, FIG. 63 is an exemplary cross sectionalschematic view of the main portion in the third manufacturing step, FIG.64 is an exemplary cross sectional schematic view of the main portion inthe fourth manufacturing step, and FIG. 65 is an exemplary crosssectional schematic view of the main portion in the fifth manufacturingstep. Hereinafter, an example of the steps of manufacturing thenonvolatile memory will be sequentially described with reference toFIGS. 61 to 65.

First, as illustrated in FIG. 61, a resist pattern 5 v, in which anelement region 40 b of the memory transistor 40C (FIG. 65) is opened andan element region 50 b of the logic transistor 50 (FIG. 65) and theelement region 30 b of the I/O transistor 30 (FIG. 65) are covered, isformed on the semiconductor substrate 2. With the resist pattern 5 vused as a mask, a predetermined impurity implantation is performed onthe semiconductor substrate 2 of the element region 40 b. For example,germanium is implanted under the conditions: the accelerating energy of30 keV and the dose amount of 5×10¹⁴ cm⁻². Carbon is implanted under theconditions: the accelerating energy of 5 keV and the dose amount of5×10¹⁴ cm⁻². Boron is implanted under the conditions: the acceleratingenergy of 20 keV and the dose amount of 4×10¹³ cm⁻². With these impurityimplantations, the relatively-high concentration impurity region 47 (SCRlayer) of the memory transistor 40C is formed.

Next, as illustrated in FIG. 62, a resist pattern 5 w, in which theelement region 50 b of the logic transistor 50 is opened and the elementregion 40 b of the memory transistor 40C and the element region 30 b ofthe I/O transistor 30 are covered, is formed on the semiconductorsubstrate 2. With the resist pattern 5 w used as a mask, a predeterminedimpurity implantation is performed on the semiconductor substrate 2 ofthe element region 50 b. For example, germanium is implanted under theconditions: the accelerating energy of 30 keV and the dose amount of5×10¹⁴ cm⁻². Carbon is implanted under the conditions: the acceleratingenergy of 5 keV and the dose amount of 5×10¹⁴ cm⁻². Boron is implantedunder the conditions: the accelerating energy of 20 keV and the doseamount of 5×10¹² cm⁻². Boron fluoride is implanted under the conditions:the accelerating energy of 10 keV and the dose amount of 1.5×10¹² cm⁻².With the impurity implantation, the relatively-high concentrationimpurity region 57 (SCR layer) of the logic transistor 50 is formed.

Next, as illustrated in FIG. 63, a semiconductor material is epitaxiallygrown on the semiconductor substrate 2 to form a semiconductor layer 8 c(non-doped layer) on the impurity region 47 of the element region 40 band on the impurity region 57 of the element region 50 b. The channelregion 46 of the memory transistor 40C and a channel region 56 of thelogic transistor 50 are formed in the semiconductor layer 8 c. Notethat, although a semiconductor layer similar to the semiconductor layer8 c of the element region 40 b and element region 50 b is formed also inthe element region 30 b due to the epitaxial growth, the semiconductorlayer will be described as the layer integrated into the semiconductorsubstrate 2 for convenience here. After formation of the semiconductorlayer 8 c, an element isolating region 3 is formed which defines theelement region 40 b, the element region 30 b, and the element region 50b, as illustrated in FIG. 63.

Next, the impurity implantation for adjusting each threshold voltage ofthe I/O transistor 30 and the logic transistor 50 is performed on thesemiconductor substrate 2 of the element region 30 b and element region50 b. Subsequently, by thermal oxidation, as illustrated in FIG. 64, thegate insulating film 31, gate insulating film 41, and gate insulatingfilm 51 each having a predetermined film thickness are formed in theelement region 30 b, in the element region 40 b, and in the elementregion 50 b, respectively. For example, the gate insulating film 31 andgate insulating film 41 each having the film thickness of 7 nm and thegate insulating film 51 having the film thickness of 1.5 nm are formed.Next, the gate electrode 32, gate electrode 42, and gate electrode 52are formed by forming and patterning polysilicon.

Next, by the impurity implantation under a predetermined condition, asillustrated in FIG. 64, the LDD regions 45 a and 45 b, the LDD regions35 a and 35 b, and the LDD regions 55 a and 55 b are formed. Forexample, phosphorus is implanted from four directions under theconditions: the accelerating energy of 35 keV, the dose amount of2.5×10¹² cm⁻², and the tilt angle of 28°, to form the LDD regions 45 aand 45 b and LDD regions 35 a and 35 b. Arsenic is implanted two timesunder the conditions: the accelerating energy of 1.5 keV, the doseamount of 2.5×10¹⁴ cm⁻², and the tilt angle of 0°, to form the LDDregions 55 a and 55 b. Thus, the structure as illustrated in FIG. 64 isobtained. The channel region 36 of the I/O transistor 30 is formedbetween the LDD regions 35 a and 35 b. The channel region 46 of thememory transistor 40C is formed between the LDD regions 45 a and 45 b.The channel region 56 of the logic transistor 50 is formed between theLDD regions 55 a and 55 b.

Next, by the formation and etchback of an insulating film, asillustrated in FIG. 65, the sidewall insulating film 33, sidewallinsulating film 43, and sidewall insulating film 53 are formed on eachsidewall of the gate electrode 32, gate electrode 42, and gate electrode52. For example, an oxide film 101 of silicon oxide or the like havingthe film thickness of 5 nm and a nitride film 102 of silicon nitride orthe like having the film thickness of 70 nm are sequentially formed andetched back, thereby forming the sidewall insulating film 33, sidewallinsulating film 43, and sidewall insulating film 53. Note that, theoxide film 101 having a different film thickness may be adopted for thesidewall insulating film 43 of the memory transistor 40C and for thesidewall insulating film 53 of the logic transistor 50. For example, theoxide film 101 of the sidewall insulating film 43 of the memorytransistor 40C is made thinner than the oxide film 101 of the sidewallinsulating film 53 of the logic transistor 50. Thus, in the memorytransistor 40C, the injection efficiency of hot carriers into thenitride film 102 is improved and the programming speed is improved.

Next, by the impurity implantation under a predetermined condition, asillustrated in FIG. 65, the impurity regions 34 a and 34 b, impurityregions 44 a and 44 b, and impurity regions 54 a and 54 b each servingas the SD region of each of the I/O transistor 30, memory transistor40C, and logic transistor 50 are formed. For example, phosphorus isimplanted under the conditions: the accelerating energy of 8 keV and thedose amount of 1.2×10¹⁶ cm⁻² to form the impurity regions 34 a and 34 b,impurity regions 44 a and 44 b, and impurity regions 54 a and 54 b.

With the above-described manufacturing steps, a nonvolatile memory 80 ahaving the I/O transistor 30, memory transistor 40C, and logictransistor 50 mixedly mounted on the common semiconductor substrate 2 isobtained. Thereafter, the formation of an interlayer insulating film,the formation of a plug, and the formation of an upper wiring layerincluding the conductors, such as a wiring and a via, and the like areperformed.

Another example of the configuration of and method for manufacturing anonvolatile memory using the memory transistor 40C (90 a, or the like)will be further described with reference to FIGS. 66 to 71.

FIGS. 66 to 71 illustrate another example of the method formanufacturing the nonvolatile memory. Here, FIG. 66 is an exemplarycross sectional schematic view of a main portion in the firstmanufacturing step, FIG. 67 is an exemplary cross sectional schematicview of the main portion in the second manufacturing step, FIG. 68 is anexemplary cross sectional schematic view of the main portion in thethird manufacturing step, FIG. 69 is an exemplary cross sectionalschematic view of the main portion in the fourth manufacturing step,FIG. 70 is an exemplary cross sectional schematic view of the mainportion in the fifth manufacturing step, and FIG. 71 is an exemplarycross sectional schematic view of the main portion in the sixthmanufacturing step. Hereinafter, an example of the steps ofmanufacturing the nonvolatile memory will be sequentially described withreference to FIGS. 66 to 71.

In this example, after the formation of the gate insulating film 31,gate insulating film 41, and gate insulating film 51 described in thesteps of the above FIGS. 61 to 63 and the steps of the above FIG. 64, apolysilicon 4 is first formed as illustrated in FIG. 66.

Next, as illustrated in FIG. 67, a predetermined resist pattern 5 x isformed on the polysilicon 4, and with the resist pattern 5 x used as amask, the polysilicon 4 is etched to form the gate electrode 42 of thememory transistor 40C.

Next, the resist pattern 5 x is removed, and with the gate electrode 42and polysilicon 4 remaining on the semiconductor substrate 2 used as amask, a predetermined impurity implantation is performed on thesemiconductor substrate 2 of the element region 40 b to form the LDDregions 45 a and 45 b as illustrated in FIG. 68. For example, phosphorusis implanted from four directions under the conditions: the acceleratingenergy of 35 keV, the dose amount of 2.5×10¹² cm⁻², and the tilt angleof 28°, to form the LDD regions 45 a and 45 b. The channel region 46 ofthe memory transistor 40C is formed between the LDD regions 45 a and 45b.

Next, by the formation and etchback of an insulating film, asillustrated in FIG. 69, the sidewall insulating film 43 is formed on thesidewall of the gate electrode 42. For example, an oxide film 101 ofsilicon oxide or the like having the film thickness of 5 nm and anitride film 102 of silicon nitride or the like having the filmthickness of 70 nm are sequentially formed and etched back, therebyforming the sidewall insulating film 43. Note that, the sidewallinsulating film 43 is similarly formed also on the sidewall of thepolysilicon 4 other than the gate electrode 42 and above thesemiconductor substrate 2 (above the element isolating region 3).

Next, as illustrated in FIG. 70, a predetermined resist pattern 5 y isformed, and with the resist pattern 5 y used as a mask, the polysilicon4 is etched to form the gate electrode 32 of the I/O transistor 30 andthe gate electrode 52 of the logic transistor 50. Note that, FIG. 70illustrates a form in which a part (edge) of the polysilicon 4 alsoremains on the element isolating region 3.

Next, by the impurity implantation under a predetermined condition, asillustrated in FIG. 71, the LDD regions 35 a and 35 b are formed in theelement region 30 b and the LDD regions 55 a and 55 b are formed in theelement region 50 b. The channel region 36 of the I/O transistor 30 isformed between the LDD regions 35 a and 35 b, and the channel region 56of the logic transistor 50 is formed between the LDD regions 55 a and 55b.

Next, by the formation and etchback of an insulating film, asillustrated in FIG. 71, the sidewall insulating film 33 and sidewallinsulating film 53 are formed on each sidewall of the gate electrode 32and gate electrode 52. The sidewall insulating film 33 and the sidewallinsulating film 53 are formed so as to have a width that is smaller thanthe width of the sidewall insulating film 43 of the memory transistor40C. Note that, the sidewall insulating film 53 (or 33) is similarlyformed also on the sidewall of the polysilicon 4 remaining on theelement isolating region 3. Next, by the impurity implantation under apredetermined condition, as illustrated in FIG. 71, the impurity regions34 a and 34 b, impurity regions 44 a and 44 b, and impurity regions 54 aand 54 b each serving as the SD region of each of the I/O transistor 30,memory transistor 40C, and logic transistor 50 are formed.

With the above-described manufacturing steps, a nonvolatile memory 80 bhaving the I/O transistor 30, memory transistor 40C, and logictransistor 50 mixedly mounted on the common semiconductor substrate 2 isobtained. Thereafter, the formation of an interlayer insulating film,the formation of a plug, and the formation of an upper wiring layerincluding the conductors, such as a wiring and a via, and the like areperformed.

The width of the sidewall insulating film 43 of the memory transistor40C is an important parameter which affects the transistorcharacteristics of the memory transistor 40C as described above. In themanufacturing method illustrated in FIGS. 66 to 71, the width of thesidewall insulating film 43 of the memory transistor 40C may be adjustedindependently of the width of the sidewall insulating film 53 of thelogic transistor 50.

FIG. 72 is an explanatory view of the memory transistor with the SCRlayer.

As described above, in the memory transistor 40C (90 a or the like), theLDD regions 45 a and 45 b are formed by the impurity implantation into anon-doped layer or a very low concentration layer (semiconductor layer 8c to be epitaxially grown) below the sidewall insulating film 43.Therefore, the very low concentration LDD regions 45 a and 45 b arestably formed. For example, if the LDD regions 45 a and 45 b are formedso as to have a concentration equal to or less than 5×10¹⁷ cm⁻³, the LDDregions 45 a and 45 b hardly contribute to impact ionization. Therefore,for example, at an edge of the impurity region 44 b (SD region) having aconcentration higher than the LDD region 45 b, the hot carriers 49 aregenerated and injected into the sidewall insulating film 43 above theimpurity region 44 b. If there is the electric charge 49 a in thesidewall insulating film 43, the very low concentration LDD region 45 bbelow the sidewall insulating film 43 is easily modulated and thus thethreshold voltage of the memory transistor 40C will vary. Furthermore,because the conductivity type of the LDD regions 45 a and 45 b isdetermined, offsetting of the memory transistor 40C is also suppressed.Moreover, an improvement in the programming characteristics is achievedby adjusting the configuration (material, width, and the material,thickness, and the like of each layer of the stacked structure) of thesidewall insulating film 43.

The memory transistor 40C may have a configuration in which a transistor40Cb with a SONGS (semiconductor substrate 2—oxide film 43 a-nitridefilm 43 b-oxide film 43 a-gate electrode 42) structure is added to theside surface of a main body transistor 40Ca.

With the disclosed technique, a transistor exhibiting an excellentprogramming speed as a memory transistor and a semiconductor deviceincluding such a transistor may be realized.

All examples and conditional language provided herein are intended forthe pedagogical purposes of aiding the reader in understanding theinvention and the concepts contributed by the inventor to further theart, and are not to be construed as limitations to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although one or more embodiments of thepresent invention have been described in detail, it should be understoodthat various changes, substitutions, and alterations could be madehereto without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising: forming a first impurity region in a first region ofa semiconductor substrate; forming a second impurity region in a secondregion of the semiconductor substrate; forming a first channel region byan epitaxial growth above the first impurity region; forming anisolation film that separates the first region and the second region inthe semiconductor substrate; forming a first gate insulating film abovethe first region; forming a second gate insulating film above the secondregion; forming a gate electrode film above the first gate insulatingfilm and the second gate insulating film; forming a first gate electrodeof the gate electrode film above the first region remaining the gateelectrode film above the second region; forming a first sidewallinsulating film on a sidewall of the first gate electrode and above thefirst region; forming a second gate electrode of the gate electrode filmabove the second region; forming a second sidewall insulating film on asidewall of the second gate electrode and above the second region;forming a first source region and a first drain region on both sides ofthe first gate electrode above the first region; and forming a secondsource region and a second drain region on both sides of the second gateelectrode above the second region, wherein: a first transistor includingthe first impurity region, the first channel region, the first gateinsulating film, the first gate electrode, the first sidewall insulatingfilm, the first source region and the first drain region; a secondtransistor including the second impurity region, the second gateinsulating film, the second gate electrode, the second sidewallinsulating film, the second source region and the second drain region;and the first transistor storing information by accumulating charge inthe first sidewall insulating film.
 2. The method according to claim 1,further comprising forming a second channel region by the epitaxialgrowth above the second impurity region, wherein the second transistorfurther including the second channel region.
 3. The method according toclaim 1, wherein a width of the first sidewall insulating film is largerthan a width of the second sidewall insulating film.
 4. The methodaccording to claim 1, wherein the first sidewall insulating filmincludes a stacked structure of an oxide film and a nitride film.
 5. Themethod according to claim 1, wherein a thickness of the first gateinsulating film is larger than a thickness of the second gate insulatingfilm.
 6. The method according to claim 1, wherein an impurityconcentration of the first impurity region is higher than an impurityconcentration of the first channel region.
 7. The method according toclaim 2, wherein an impurity concentration of the second impurity regionis higher than an impurity concentration of the second channel region.8. The method according to claim 6, further comprising forming a thirdimpurity region below the first impurity region of the semiconductorsubstrate, wherein an impurity concentration of the third impurityregion is higher than an impurity concentration of the first channelregion.
 9. The method according to claim 7, further comprising forming afourth impurity region below the second impurity region of thesemiconductor substrate, wherein an impurity concentration of the fourthimpurity region is higher than an impurity concentration of the secondchannel region.
 10. The method according to claim 1, further comprising:forming a ground line above the semiconductor substrate, the ground linewhich extends in a first direction in planar view and is connected toone of the first source region and the first drain region; and forming abit line above the semiconductor substrate, the bit line which extendsin a second direction different from the first direction in the planarview and is connected to the other one of the first source region andthe first drain region; wherein, the forming of the first gate electrodeincludes forming the first gate electrode as a word line which extendsin the first direction in the planar view.
 11. The method according toclaim 1, wherein: the first source region and the first drain regioncontain a first impurity of a first conductivity type; and the firstimpurity region contains a second impurity of a second conductivity typedifferent from the first conductivity type.
 12. The method according toclaim 2, wherein: the second source region and the second drain regioncontain a third impurity of a third conductivity type; and the secondimpurity region contains a fourth impurity of a fourth conductivity typedifferent from the third conductivity type.
 13. The method according toclaim 1, wherein the first impurity region includes at least Boron,Germanium and Carbon.
 14. The method according to claim 2, wherein inthe forming of the first impurity region and the second impurity region,a first impurity implantation with respect to the first region and thesecond region is performed.
 15. The method according to claim 14,wherein a second impurity implantation with respect to the first regionis performed, after the first impurity implantation.
 16. The methodaccording to claim 1, wherein an impurity concentration of the firstchannel region is equal to or less than 1×10¹⁷ cm⁻³.
 17. The methodaccording to claim 1, further comprising forming a fifth impurity regionon an inner side of the first source region and the first drain regionbelow the first sidewall insulating film, the fifth impurity regionhaving a lower impurity concentration than the first source region andthe first drain region.
 18. The method according to claim 17, wherein:the first source region and the first drain region contain a fifthimpurity of a fifth conductivity type; the fifth impurity regioncontains a sixth impurity of the fifth conductivity type; and the firstimpurity region contains a seventh impurity of a sixth conductivity typedifferent from the fifth conductivity type.
 19. The method according toclaim 17, wherein an impurity concentration of the fifth impurity regionis equal to or less than 5×10¹⁷ cm⁻³.
 20. The method according to claim1, further comprising: forming a sixth impurity region in a third regionof the semiconductor substrate; forming a third gate insulating filmabove the third region; forming a third gate electrode above the thirdgate insulating film; forming a third sidewall insulating film on asidewall of the third gate electrode and above the third region; andforming a third source region and a third drain region on both sides ofthe third gate electrode in the third region; wherein: a width of thefirst sidewall insulating film is larger than a width of the secondsidewall insulating film and a width of the third sidewall insulatingfilm; and a thickness of the first gate insulating film and a thicknessof the third gate insulating film are larger than a thickness of thesecond gate insulating film.